STM32 provides a new compilation mode that greatly reduces the initial compilation time and is easier to operate.
This commit is contained in:
SSYYL
parent
04115ac1a4
commit
0f3d02f894
168 changed files with 333490 additions and 6435 deletions
5
Arduino/epd3in52/.vscode/arduino.json
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5
Arduino/epd3in52/.vscode/arduino.json
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{
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"port": "COM69",
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"board": "arduino:avr:uno",
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"sketch": "epd3in52.ino"
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}
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538
Arduino/epd3in52/.vscode/c_cpp_properties.json
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538
Arduino/epd3in52/.vscode/c_cpp_properties.json
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{
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"version": 4,
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"configurations": [
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{
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"name": "Arduino",
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"compilerPath": "D:\\Arduino\\az\\Arduino\\hardware\\tools\\avr\\bin\\avr-g++",
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"compilerArgs": [
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"-w",
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"-std=gnu++11",
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"-fpermissive",
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"-fno-exceptions",
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"-ffunction-sections",
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"-fdata-sections",
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"-fno-threadsafe-statics",
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"-Wno-error=narrowing"
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],
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"intelliSenseMode": "gcc-x64",
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"includePath": [
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"D:\\Arduino\\az\\Arduino\\hardware\\arduino\\avr\\cores\\arduino",
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"D:\\Arduino\\az\\Arduino\\hardware\\arduino\\avr\\variants\\standard",
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"D:\\Arduino\\az\\Arduino\\hardware\\arduino\\avr\\libraries\\SPI\\src",
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"d:\\arduino\\az\\arduino\\hardware\\tools\\avr\\lib\\gcc\\avr\\7.3.0\\include",
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"d:\\arduino\\az\\arduino\\hardware\\tools\\avr\\lib\\gcc\\avr\\7.3.0\\include-fixed",
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"d:\\arduino\\az\\arduino\\hardware\\tools\\avr\\avr\\include"
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],
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"forcedInclude": [
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"D:\\Arduino\\az\\Arduino\\hardware\\arduino\\avr\\cores\\arduino\\Arduino.h"
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],
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"cStandard": "c11",
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"cppStandard": "c++11",
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"defines": [
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"F_CPU=16000000L",
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"ARDUINO=10818",
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"ARDUINO_AVR_UNO",
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"ARDUINO_ARCH_AVR",
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"__DBL_MIN_EXP__=(-125)",
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"__HQ_FBIT__=15",
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"__cpp_attributes=200809",
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"__UINT_LEAST16_MAX__=0xffffU",
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"__ATOMIC_ACQUIRE=2",
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"__SFRACT_IBIT__=0",
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"__FLT_MIN__=1.17549435e-38F",
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"__GCC_IEC_559_COMPLEX=0",
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"__BUILTIN_AVR_SLEEP=1",
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"__BUILTIN_AVR_COUNTLSULLK=1",
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"__cpp_aggregate_nsdmi=201304",
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"__BUILTIN_AVR_COUNTLSULLR=1",
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"__UFRACT_MAX__=0XFFFFP-16UR",
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"__UINT_LEAST8_TYPE__=unsigned char",
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"__DQ_FBIT__=63",
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"__INTMAX_C(c)=c ## LL",
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"__ULFRACT_FBIT__=32",
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"__SACCUM_EPSILON__=0x1P-7HK",
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"__CHAR_BIT__=8",
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"__USQ_IBIT__=0",
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"__UINT8_MAX__=0xff",
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"__ACCUM_FBIT__=15",
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"__WINT_MAX__=0x7fff",
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"__FLT32_MIN_EXP__=(-125)",
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"__cpp_static_assert=200410",
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"__USFRACT_FBIT__=8",
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"__ORDER_LITTLE_ENDIAN__=1234",
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"__SIZE_MAX__=0xffffU",
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"__WCHAR_MAX__=0x7fff",
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"__LACCUM_IBIT__=32",
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"__DBL_DENORM_MIN__=double(1.40129846e-45L)",
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"__GCC_ATOMIC_CHAR_LOCK_FREE=1",
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"__GCC_IEC_559=0",
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"__FLT_EVAL_METHOD__=0",
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"__BUILTIN_AVR_LLKBITS=1",
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"__cpp_binary_literals=201304",
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"__LLACCUM_MAX__=0X7FFFFFFFFFFFFFFFP-47LLK",
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"__GCC_ATOMIC_CHAR32_T_LOCK_FREE=1",
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"__BUILTIN_AVR_HKBITS=1",
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"__BUILTIN_AVR_BITSLLK=1",
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"__FRACT_FBIT__=15",
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"__BUILTIN_AVR_BITSLLR=1",
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"__cpp_variadic_templates=200704",
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"__UINT_FAST64_MAX__=0xffffffffffffffffULL",
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"__SIG_ATOMIC_TYPE__=char",
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"__BUILTIN_AVR_UHKBITS=1",
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"__UACCUM_FBIT__=16",
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"__DBL_MIN_10_EXP__=(-37)",
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"__FINITE_MATH_ONLY__=0",
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"__cpp_variable_templates=201304",
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"__LFRACT_IBIT__=0",
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"__GNUC_PATCHLEVEL__=0",
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"__FLT32_HAS_DENORM__=1",
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"__LFRACT_MAX__=0X7FFFFFFFP-31LR",
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"__UINT_FAST8_MAX__=0xff",
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"__has_include(STR)=__has_include__(STR)",
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"__DEC64_MAX_EXP__=385",
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"__INT8_C(c)=c",
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"__INT_LEAST8_WIDTH__=8",
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"__UINT_LEAST64_MAX__=0xffffffffffffffffULL",
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"__SA_FBIT__=15",
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"__SHRT_MAX__=0x7fff",
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"__LDBL_MAX__=3.40282347e+38L",
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"__FRACT_MAX__=0X7FFFP-15R",
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"__UFRACT_FBIT__=16",
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"__UFRACT_MIN__=0.0UR",
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"__UINT_LEAST8_MAX__=0xff",
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"__GCC_ATOMIC_BOOL_LOCK_FREE=1",
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"__UINTMAX_TYPE__=long long unsigned int",
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"__LLFRACT_EPSILON__=0x1P-63LLR",
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"__BUILTIN_AVR_DELAY_CYCLES=1",
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"__DEC32_EPSILON__=1E-6DF",
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"__FLT_EVAL_METHOD_TS_18661_3__=0",
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"__UINT32_MAX__=0xffffffffUL",
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"__GXX_EXPERIMENTAL_CXX0X__=1",
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"__ULFRACT_MAX__=0XFFFFFFFFP-32ULR",
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"__TA_IBIT__=16",
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"__LDBL_MAX_EXP__=128",
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"__WINT_MIN__=(-__WINT_MAX__ - 1)",
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"__INT_LEAST16_WIDTH__=16",
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"__ULLFRACT_MIN__=0.0ULLR",
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"__SCHAR_MAX__=0x7f",
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"__WCHAR_MIN__=(-__WCHAR_MAX__ - 1)",
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"__INT64_C(c)=c ## LL",
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"__DBL_DIG__=6",
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"__GCC_ATOMIC_POINTER_LOCK_FREE=1",
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"__AVR_HAVE_SPH__=1",
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"__LLACCUM_MIN__=(-0X1P15LLK-0X1P15LLK)",
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"__BUILTIN_AVR_KBITS=1",
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"__BUILTIN_AVR_ABSK=1",
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"__BUILTIN_AVR_ABSR=1",
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"__SIZEOF_INT__=2",
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"__SIZEOF_POINTER__=2",
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"__GCC_ATOMIC_CHAR16_T_LOCK_FREE=1",
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"__USACCUM_IBIT__=8",
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"__USER_LABEL_PREFIX__",
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"__STDC_HOSTED__=1",
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"__LDBL_HAS_INFINITY__=1",
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"__LFRACT_MIN__=(-0.5LR-0.5LR)",
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"__HA_IBIT__=8",
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"__FLT32_DIG__=6",
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"__TQ_IBIT__=0",
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"__FLT_EPSILON__=1.19209290e-7F",
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"__GXX_WEAK__=1",
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"__SHRT_WIDTH__=16",
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"__USFRACT_IBIT__=0",
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"__LDBL_MIN__=1.17549435e-38L",
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"__FRACT_MIN__=(-0.5R-0.5R)",
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"__AVR_SFR_OFFSET__=0x20",
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"__DEC32_MAX__=9.999999E96DF",
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"__cpp_threadsafe_static_init=200806",
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"__DA_IBIT__=32",
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"__INT32_MAX__=0x7fffffffL",
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"__UQQ_FBIT__=8",
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"__INT_WIDTH__=16",
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"__SIZEOF_LONG__=4",
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"__UACCUM_MAX__=0XFFFFFFFFP-16UK",
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"__UINT16_C(c)=c ## U",
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"__PTRDIFF_WIDTH__=16",
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"__DECIMAL_DIG__=9",
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"__LFRACT_EPSILON__=0x1P-31LR",
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"__AVR_2_BYTE_PC__=1",
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"__ULFRACT_MIN__=0.0ULR",
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"__INTMAX_WIDTH__=64",
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"__has_include_next(STR)=__has_include_next__(STR)",
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"__BUILTIN_AVR_ULLRBITS=1",
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"__LDBL_HAS_QUIET_NAN__=1",
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"__ULACCUM_IBIT__=32",
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"__UACCUM_EPSILON__=0x1P-16UK",
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"__BUILTIN_AVR_SEI=1",
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"__GNUC__=7",
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"__ULLACCUM_MAX__=0XFFFFFFFFFFFFFFFFP-48ULLK",
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"__cpp_delegating_constructors=200604",
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"__HQ_IBIT__=0",
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"__BUILTIN_AVR_SWAP=1",
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"__FLT_HAS_DENORM__=1",
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"__SIZEOF_LONG_DOUBLE__=4",
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"__BIGGEST_ALIGNMENT__=1",
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"__STDC_UTF_16__=1",
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"__UINT24_MAX__=16777215UL",
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"__BUILTIN_AVR_NOP=1",
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"__GNUC_STDC_INLINE__=1",
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"__DQ_IBIT__=0",
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"__FLT32_HAS_INFINITY__=1",
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"__DBL_MAX__=double(3.40282347e+38L)",
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"__ULFRACT_IBIT__=0",
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"__cpp_raw_strings=200710",
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"__INT_FAST32_MAX__=0x7fffffffL",
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"__DBL_HAS_INFINITY__=1",
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"__INT64_MAX__=0x7fffffffffffffffLL",
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"__ACCUM_IBIT__=16",
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"__DEC32_MIN_EXP__=(-94)",
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"__BUILTIN_AVR_UKBITS=1",
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"__INTPTR_WIDTH__=16",
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"__BUILTIN_AVR_FMULSU=1",
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"__LACCUM_MAX__=0X7FFFFFFFFFFFFFFFP-31LK",
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"__INT_FAST16_TYPE__=int",
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"__LDBL_HAS_DENORM__=1",
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"__BUILTIN_AVR_BITSK=1",
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"__BUILTIN_AVR_BITSR=1",
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"__cplusplus=201402L",
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"__cpp_ref_qualifiers=200710",
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"__DEC128_MAX__=9.999999999999999999999999999999999E6144DL",
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"__INT_LEAST32_MAX__=0x7fffffffL",
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"__USING_SJLJ_EXCEPTIONS__=1",
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"__DEC32_MIN__=1E-95DF",
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"__ACCUM_MAX__=0X7FFFFFFFP-15K",
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"__DEPRECATED=1",
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"__cpp_rvalue_references=200610",
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"__DBL_MAX_EXP__=128",
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"__USACCUM_EPSILON__=0x1P-8UHK",
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"__WCHAR_WIDTH__=16",
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"__FLT32_MAX__=3.40282347e+38F32",
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"__DEC128_EPSILON__=1E-33DL",
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"__SFRACT_MAX__=0X7FP-7HR",
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"__FRACT_IBIT__=0",
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"__PTRDIFF_MAX__=0x7fff",
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"__UACCUM_MIN__=0.0UK",
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"__UACCUM_IBIT__=16",
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"__BUILTIN_AVR_NOPS=1",
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"__BUILTIN_AVR_WDR=1",
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"__FLT32_HAS_QUIET_NAN__=1",
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"__GNUG__=7",
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"__LONG_LONG_MAX__=0x7fffffffffffffffLL",
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"__SIZEOF_SIZE_T__=2",
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"__ULACCUM_MAX__=0XFFFFFFFFFFFFFFFFP-32ULK",
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"__cpp_rvalue_reference=200610",
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"__cpp_nsdmi=200809",
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"__SIZEOF_WINT_T__=2",
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"__LONG_LONG_WIDTH__=64",
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"__cpp_initializer_lists=200806",
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"__FLT32_MAX_EXP__=128",
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"__SA_IBIT__=16",
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"__ULLACCUM_MIN__=0.0ULLK",
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"__BUILTIN_AVR_ROUNDUHK=1",
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"__BUILTIN_AVR_ROUNDUHR=1",
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"__cpp_hex_float=201603",
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"__GXX_ABI_VERSION=1011",
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"__INT24_MAX__=8388607L",
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"__UTA_FBIT__=48",
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"__FLT_MIN_EXP__=(-125)",
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"__USFRACT_MAX__=0XFFP-8UHR",
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"__UFRACT_IBIT__=0",
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"__BUILTIN_AVR_ROUNDFX=1",
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"__BUILTIN_AVR_ROUNDULK=1",
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"__BUILTIN_AVR_ROUNDULR=1",
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"__cpp_lambdas=200907",
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"__BUILTIN_AVR_COUNTLSLLK=1",
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"__BUILTIN_AVR_COUNTLSLLR=1",
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"__BUILTIN_AVR_ROUNDHK=1",
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"__INT_FAST64_TYPE__=long long int",
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"__BUILTIN_AVR_ROUNDHR=1",
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"__DBL_MIN__=double(1.17549435e-38L)",
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"__BUILTIN_AVR_COUNTLSK=1",
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"__BUILTIN_AVR_ROUNDLK=1",
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"__BUILTIN_AVR_COUNTLSR=1",
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"__BUILTIN_AVR_ROUNDLR=1",
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"__LACCUM_MIN__=(-0X1P31LK-0X1P31LK)",
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"__ULLACCUM_FBIT__=48",
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"__BUILTIN_AVR_LKBITS=1",
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"__ULLFRACT_EPSILON__=0x1P-64ULLR",
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"__DEC128_MIN__=1E-6143DL",
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"__REGISTER_PREFIX__",
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"__UINT16_MAX__=0xffffU",
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"__DBL_HAS_DENORM__=1",
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"__BUILTIN_AVR_ULKBITS=1",
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"__ACCUM_MIN__=(-0X1P15K-0X1P15K)",
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"__AVR_ARCH__=2",
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"__SQ_IBIT__=0",
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"__FLT32_MIN__=1.17549435e-38F32",
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"__UINT8_TYPE__=unsigned char",
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"__BUILTIN_AVR_ROUNDUK=1",
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"__BUILTIN_AVR_ROUNDUR=1",
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"__UHA_FBIT__=8",
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"__NO_INLINE__=1",
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"__SFRACT_MIN__=(-0.5HR-0.5HR)",
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"__UTQ_FBIT__=128",
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"__FLT_MANT_DIG__=24",
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"__LDBL_DECIMAL_DIG__=9",
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"__VERSION__=\"7.3.0\"",
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"__UINT64_C(c)=c ## ULL",
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"__ULLFRACT_FBIT__=64",
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"__cpp_unicode_characters=200704",
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"__FRACT_EPSILON__=0x1P-15R",
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"__ULACCUM_MIN__=0.0ULK",
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"__UDA_FBIT__=32",
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"__cpp_decltype_auto=201304",
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"__LLACCUM_EPSILON__=0x1P-47LLK",
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"__GCC_ATOMIC_INT_LOCK_FREE=1",
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"__FLT32_MANT_DIG__=24",
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"__BUILTIN_AVR_BITSUHK=1",
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"__BUILTIN_AVR_BITSUHR=1",
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"__FLOAT_WORD_ORDER__=__ORDER_LITTLE_ENDIAN__",
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|
"__USFRACT_MIN__=0.0UHR",
|
||||||
|
"__BUILTIN_AVR_BITSULK=1",
|
||||||
|
"__ULLACCUM_IBIT__=16",
|
||||||
|
"__BUILTIN_AVR_BITSULR=1",
|
||||||
|
"__UQQ_IBIT__=0",
|
||||||
|
"__BUILTIN_AVR_LLRBITS=1",
|
||||||
|
"__SCHAR_WIDTH__=8",
|
||||||
|
"__BUILTIN_AVR_BITSULLK=1",
|
||||||
|
"__BUILTIN_AVR_BITSULLR=1",
|
||||||
|
"__INT32_C(c)=c ## L",
|
||||||
|
"__DEC64_EPSILON__=1E-15DD",
|
||||||
|
"__ORDER_PDP_ENDIAN__=3412",
|
||||||
|
"__DEC128_MIN_EXP__=(-6142)",
|
||||||
|
"__UHQ_FBIT__=16",
|
||||||
|
"__LLACCUM_FBIT__=47",
|
||||||
|
"__FLT32_MAX_10_EXP__=38",
|
||||||
|
"__BUILTIN_AVR_ROUNDULLK=1",
|
||||||
|
"__BUILTIN_AVR_ROUNDULLR=1",
|
||||||
|
"__INT_FAST32_TYPE__=long int",
|
||||||
|
"__BUILTIN_AVR_HRBITS=1",
|
||||||
|
"__UINT_LEAST16_TYPE__=unsigned int",
|
||||||
|
"__BUILTIN_AVR_UHRBITS=1",
|
||||||
|
"__INT16_MAX__=0x7fff",
|
||||||
|
"__SIZE_TYPE__=unsigned int",
|
||||||
|
"__UINT64_MAX__=0xffffffffffffffffULL",
|
||||||
|
"__UDQ_FBIT__=64",
|
||||||
|
"__INT8_TYPE__=signed char",
|
||||||
|
"__cpp_digit_separators=201309",
|
||||||
|
"__ELF__=1",
|
||||||
|
"__ULFRACT_EPSILON__=0x1P-32ULR",
|
||||||
|
"__LLFRACT_FBIT__=63",
|
||||||
|
"__FLT_RADIX__=2",
|
||||||
|
"__INT_LEAST16_TYPE__=int",
|
||||||
|
"__BUILTIN_AVR_ABSFX=1",
|
||||||
|
"__LDBL_EPSILON__=1.19209290e-7L",
|
||||||
|
"__UINTMAX_C(c)=c ## ULL",
|
||||||
|
"__INT24_MIN__=(-__INT24_MAX__-1)",
|
||||||
|
"__SACCUM_MAX__=0X7FFFP-7HK",
|
||||||
|
"__BUILTIN_AVR_ABSHR=1",
|
||||||
|
"__SIG_ATOMIC_MAX__=0x7f",
|
||||||
|
"__GCC_ATOMIC_WCHAR_T_LOCK_FREE=1",
|
||||||
|
"__cpp_sized_deallocation=201309",
|
||||||
|
"__SIZEOF_PTRDIFF_T__=2",
|
||||||
|
"__AVR=1",
|
||||||
|
"__BUILTIN_AVR_ABSLK=1",
|
||||||
|
"__BUILTIN_AVR_ABSLR=1",
|
||||||
|
"__LACCUM_EPSILON__=0x1P-31LK",
|
||||||
|
"__DEC32_SUBNORMAL_MIN__=0.000001E-95DF",
|
||||||
|
"__INT_FAST16_MAX__=0x7fff",
|
||||||
|
"__UINT_FAST32_MAX__=0xffffffffUL",
|
||||||
|
"__UINT_LEAST64_TYPE__=long long unsigned int",
|
||||||
|
"__USACCUM_MAX__=0XFFFFP-8UHK",
|
||||||
|
"__SFRACT_EPSILON__=0x1P-7HR",
|
||||||
|
"__FLT_HAS_QUIET_NAN__=1",
|
||||||
|
"__FLT_MAX_10_EXP__=38",
|
||||||
|
"__LONG_MAX__=0x7fffffffL",
|
||||||
|
"__DEC128_SUBNORMAL_MIN__=0.000000000000000000000000000000001E-6143DL",
|
||||||
|
"__FLT_HAS_INFINITY__=1",
|
||||||
|
"__cpp_unicode_literals=200710",
|
||||||
|
"__USA_FBIT__=16",
|
||||||
|
"__UINT_FAST16_TYPE__=unsigned int",
|
||||||
|
"__DEC64_MAX__=9.999999999999999E384DD",
|
||||||
|
"__INT_FAST32_WIDTH__=32",
|
||||||
|
"__BUILTIN_AVR_RBITS=1",
|
||||||
|
"__CHAR16_TYPE__=unsigned int",
|
||||||
|
"__PRAGMA_REDEFINE_EXTNAME=1",
|
||||||
|
"__SIZE_WIDTH__=16",
|
||||||
|
"__INT_LEAST16_MAX__=0x7fff",
|
||||||
|
"__DEC64_MANT_DIG__=16",
|
||||||
|
"__UINT_LEAST32_MAX__=0xffffffffUL",
|
||||||
|
"__SACCUM_FBIT__=7",
|
||||||
|
"__FLT32_DENORM_MIN__=1.40129846e-45F32",
|
||||||
|
"__GCC_ATOMIC_LONG_LOCK_FREE=1",
|
||||||
|
"__SIG_ATOMIC_WIDTH__=8",
|
||||||
|
"__INT_LEAST64_TYPE__=long long int",
|
||||||
|
"__INT16_TYPE__=int",
|
||||||
|
"__INT_LEAST8_TYPE__=signed char",
|
||||||
|
"__SQ_FBIT__=31",
|
||||||
|
"__DEC32_MAX_EXP__=97",
|
||||||
|
"__INT_FAST8_MAX__=0x7f",
|
||||||
|
"__INTPTR_MAX__=0x7fff",
|
||||||
|
"__QQ_FBIT__=7",
|
||||||
|
"__cpp_range_based_for=200907",
|
||||||
|
"__UTA_IBIT__=16",
|
||||||
|
"__AVR_ERRATA_SKIP__=1",
|
||||||
|
"__FLT32_MIN_10_EXP__=(-37)",
|
||||||
|
"__LDBL_MANT_DIG__=24",
|
||||||
|
"__SFRACT_FBIT__=7",
|
||||||
|
"__SACCUM_MIN__=(-0X1P7HK-0X1P7HK)",
|
||||||
|
"__DBL_HAS_QUIET_NAN__=1",
|
||||||
|
"__SIG_ATOMIC_MIN__=(-__SIG_ATOMIC_MAX__ - 1)",
|
||||||
|
"AVR=1",
|
||||||
|
"__BUILTIN_AVR_FMULS=1",
|
||||||
|
"__cpp_return_type_deduction=201304",
|
||||||
|
"__INTPTR_TYPE__=int",
|
||||||
|
"__UINT16_TYPE__=unsigned int",
|
||||||
|
"__WCHAR_TYPE__=int",
|
||||||
|
"__SIZEOF_FLOAT__=4",
|
||||||
|
"__AVR__=1",
|
||||||
|
"__BUILTIN_AVR_INSERT_BITS=1",
|
||||||
|
"__USQ_FBIT__=32",
|
||||||
|
"__UINTPTR_MAX__=0xffffU",
|
||||||
|
"__INT_FAST64_WIDTH__=64",
|
||||||
|
"__DEC64_MIN_EXP__=(-382)",
|
||||||
|
"__cpp_decltype=200707",
|
||||||
|
"__FLT32_DECIMAL_DIG__=9",
|
||||||
|
"__INT_FAST64_MAX__=0x7fffffffffffffffLL",
|
||||||
|
"__GCC_ATOMIC_TEST_AND_SET_TRUEVAL=1",
|
||||||
|
"__FLT_DIG__=6",
|
||||||
|
"__UINT_FAST64_TYPE__=long long unsigned int",
|
||||||
|
"__BUILTIN_AVR_BITSHK=1",
|
||||||
|
"__BUILTIN_AVR_BITSHR=1",
|
||||||
|
"__INT_MAX__=0x7fff",
|
||||||
|
"__LACCUM_FBIT__=31",
|
||||||
|
"__USACCUM_MIN__=0.0UHK",
|
||||||
|
"__UHA_IBIT__=8",
|
||||||
|
"__INT64_TYPE__=long long int",
|
||||||
|
"__BUILTIN_AVR_BITSLK=1",
|
||||||
|
"__BUILTIN_AVR_BITSLR=1",
|
||||||
|
"__FLT_MAX_EXP__=128",
|
||||||
|
"__UTQ_IBIT__=0",
|
||||||
|
"__DBL_MANT_DIG__=24",
|
||||||
|
"__cpp_inheriting_constructors=201511",
|
||||||
|
"__BUILTIN_AVR_ULLKBITS=1",
|
||||||
|
"__INT_LEAST64_MAX__=0x7fffffffffffffffLL",
|
||||||
|
"__DEC64_MIN__=1E-383DD",
|
||||||
|
"__WINT_TYPE__=int",
|
||||||
|
"__UINT_LEAST32_TYPE__=long unsigned int",
|
||||||
|
"__SIZEOF_SHORT__=2",
|
||||||
|
"__ULLFRACT_IBIT__=0",
|
||||||
|
"__LDBL_MIN_EXP__=(-125)",
|
||||||
|
"__UDA_IBIT__=32",
|
||||||
|
"__WINT_WIDTH__=16",
|
||||||
|
"__INT_LEAST8_MAX__=0x7f",
|
||||||
|
"__LFRACT_FBIT__=31",
|
||||||
|
"__LDBL_MAX_10_EXP__=38",
|
||||||
|
"__ATOMIC_RELAXED=0",
|
||||||
|
"__DBL_EPSILON__=double(1.19209290e-7L)",
|
||||||
|
"__BUILTIN_AVR_BITSUK=1",
|
||||||
|
"__BUILTIN_AVR_BITSUR=1",
|
||||||
|
"__UINT8_C(c)=c",
|
||||||
|
"__INT_LEAST32_TYPE__=long int",
|
||||||
|
"__BUILTIN_AVR_URBITS=1",
|
||||||
|
"__SIZEOF_WCHAR_T__=2",
|
||||||
|
"__LLFRACT_MAX__=0X7FFFFFFFFFFFFFFFP-63LLR",
|
||||||
|
"__TQ_FBIT__=127",
|
||||||
|
"__INT_FAST8_TYPE__=signed char",
|
||||||
|
"__ULLACCUM_EPSILON__=0x1P-48ULLK",
|
||||||
|
"__BUILTIN_AVR_ROUNDK=1",
|
||||||
|
"__BUILTIN_AVR_ROUNDR=1",
|
||||||
|
"__UHQ_IBIT__=0",
|
||||||
|
"__LLACCUM_IBIT__=16",
|
||||||
|
"__FLT32_EPSILON__=1.19209290e-7F32",
|
||||||
|
"__DBL_DECIMAL_DIG__=9",
|
||||||
|
"__STDC_UTF_32__=1",
|
||||||
|
"__INT_FAST8_WIDTH__=8",
|
||||||
|
"__DEC_EVAL_METHOD__=2",
|
||||||
|
"__TA_FBIT__=47",
|
||||||
|
"__UDQ_IBIT__=0",
|
||||||
|
"__ORDER_BIG_ENDIAN__=4321",
|
||||||
|
"__cpp_runtime_arrays=198712",
|
||||||
|
"__WITH_AVRLIBC__=1",
|
||||||
|
"__UINT64_TYPE__=long long unsigned int",
|
||||||
|
"__ACCUM_EPSILON__=0x1P-15K",
|
||||||
|
"__UINT32_C(c)=c ## UL",
|
||||||
|
"__BUILTIN_AVR_COUNTLSUHK=1",
|
||||||
|
"__INTMAX_MAX__=0x7fffffffffffffffLL",
|
||||||
|
"__cpp_alias_templates=200704",
|
||||||
|
"__BUILTIN_AVR_COUNTLSUHR=1",
|
||||||
|
"__BYTE_ORDER__=__ORDER_LITTLE_ENDIAN__",
|
||||||
|
"__FLT_DENORM_MIN__=1.40129846e-45F",
|
||||||
|
"__LLFRACT_IBIT__=0",
|
||||||
|
"__INT8_MAX__=0x7f",
|
||||||
|
"__LONG_WIDTH__=32",
|
||||||
|
"__UINT_FAST32_TYPE__=long unsigned int",
|
||||||
|
"__CHAR32_TYPE__=long unsigned int",
|
||||||
|
"__BUILTIN_AVR_COUNTLSULK=1",
|
||||||
|
"__BUILTIN_AVR_COUNTLSULR=1",
|
||||||
|
"__FLT_MAX__=3.40282347e+38F",
|
||||||
|
"__cpp_constexpr=201304",
|
||||||
|
"__USACCUM_FBIT__=8",
|
||||||
|
"__BUILTIN_AVR_COUNTLSFX=1",
|
||||||
|
"__INT32_TYPE__=long int",
|
||||||
|
"__SIZEOF_DOUBLE__=4",
|
||||||
|
"__FLT_MIN_10_EXP__=(-37)",
|
||||||
|
"__UFRACT_EPSILON__=0x1P-16UR",
|
||||||
|
"__INT_LEAST32_WIDTH__=32",
|
||||||
|
"__BUILTIN_AVR_COUNTLSHK=1",
|
||||||
|
"__BUILTIN_AVR_COUNTLSHR=1",
|
||||||
|
"__INTMAX_TYPE__=long long int",
|
||||||
|
"__BUILTIN_AVR_ABSLLK=1",
|
||||||
|
"__BUILTIN_AVR_ABSLLR=1",
|
||||||
|
"__DEC128_MAX_EXP__=6145",
|
||||||
|
"__AVR_HAVE_16BIT_SP__=1",
|
||||||
|
"__ATOMIC_CONSUME=1",
|
||||||
|
"__GNUC_MINOR__=3",
|
||||||
|
"__INT_FAST16_WIDTH__=16",
|
||||||
|
"__UINTMAX_MAX__=0xffffffffffffffffULL",
|
||||||
|
"__DEC32_MANT_DIG__=7",
|
||||||
|
"__HA_FBIT__=7",
|
||||||
|
"__BUILTIN_AVR_COUNTLSLK=1",
|
||||||
|
"__BUILTIN_AVR_COUNTLSLR=1",
|
||||||
|
"__BUILTIN_AVR_CLI=1",
|
||||||
|
"__DBL_MAX_10_EXP__=38",
|
||||||
|
"__LDBL_DENORM_MIN__=1.40129846e-45L",
|
||||||
|
"__INT16_C(c)=c",
|
||||||
|
"__cpp_generic_lambdas=201304",
|
||||||
|
"__STDC__=1",
|
||||||
|
"__PTRDIFF_TYPE__=int",
|
||||||
|
"__LLFRACT_MIN__=(-0.5LLR-0.5LLR)",
|
||||||
|
"__BUILTIN_AVR_LRBITS=1",
|
||||||
|
"__ATOMIC_SEQ_CST=5",
|
||||||
|
"__DA_FBIT__=31",
|
||||||
|
"__UINT32_TYPE__=long unsigned int",
|
||||||
|
"__BUILTIN_AVR_ROUNDLLK=1",
|
||||||
|
"__UINTPTR_TYPE__=unsigned int",
|
||||||
|
"__BUILTIN_AVR_ROUNDLLR=1",
|
||||||
|
"__USA_IBIT__=16",
|
||||||
|
"__BUILTIN_AVR_ULRBITS=1",
|
||||||
|
"__DEC64_SUBNORMAL_MIN__=0.000000000000001E-383DD",
|
||||||
|
"__DEC128_MANT_DIG__=34",
|
||||||
|
"__LDBL_MIN_10_EXP__=(-37)",
|
||||||
|
"__BUILTIN_AVR_COUNTLSUK=1",
|
||||||
|
"__BUILTIN_AVR_COUNTLSUR=1",
|
||||||
|
"__SIZEOF_LONG_LONG__=8",
|
||||||
|
"__ULACCUM_EPSILON__=0x1P-32ULK",
|
||||||
|
"__cpp_user_defined_literals=200809",
|
||||||
|
"__SACCUM_IBIT__=8",
|
||||||
|
"__GCC_ATOMIC_LLONG_LOCK_FREE=1",
|
||||||
|
"__LDBL_DIG__=6",
|
||||||
|
"__FLT_DECIMAL_DIG__=9",
|
||||||
|
"__UINT_FAST16_MAX__=0xffffU",
|
||||||
|
"__GCC_ATOMIC_SHORT_LOCK_FREE=1",
|
||||||
|
"__BUILTIN_AVR_ABSHK=1",
|
||||||
|
"__BUILTIN_AVR_FLASH_SEGMENT=1",
|
||||||
|
"__INT_LEAST64_WIDTH__=64",
|
||||||
|
"__ULLFRACT_MAX__=0XFFFFFFFFFFFFFFFFP-64ULLR",
|
||||||
|
"__UINT_FAST8_TYPE__=unsigned char",
|
||||||
|
"__USFRACT_EPSILON__=0x1P-8UHR",
|
||||||
|
"__ULACCUM_FBIT__=32",
|
||||||
|
"__QQ_IBIT__=0",
|
||||||
|
"__cpp_init_captures=201304",
|
||||||
|
"__ATOMIC_ACQ_REL=4",
|
||||||
|
"__ATOMIC_RELEASE=3",
|
||||||
|
"__BUILTIN_AVR_FMUL=1",
|
||||||
|
"USBCON"
|
||||||
|
]
|
||||||
|
}
|
||||||
|
]
|
||||||
|
}
|
||||||
7
STM32/ReadMe.txt
Normal file
7
STM32/ReadMe.txt
Normal file
|
|
@ -0,0 +1,7 @@
|
||||||
|
中文：
|
||||||
|
简单使用：
|
||||||
|
打开工程后点击编译栏的下拉框，选择对应屏幕的目标，然后点击编译。
|
||||||
|
|
||||||
|
English：
|
||||||
|
Easy to use:
|
||||||
|
After opening the project, click the drop-down box in the Compile bar, select the target of the corresponding screen, and then click Compile.
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,36 @@
|
||||||
|
// File: STM32F101_102_103_105_107.dbgconf
|
||||||
|
// Version: 1.0.0
|
||||||
|
// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008)
|
||||||
|
// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets
|
||||||
|
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
|
||||||
|
// <h> Debug MCU configuration register (DBGMCU_CR)
|
||||||
|
// <i> Reserved bits must be kept at reset value
|
||||||
|
// <o.30> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
|
||||||
|
// <o.29> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
|
||||||
|
// <o.28> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
|
||||||
|
// <o.27> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
|
||||||
|
// <o.26> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
|
||||||
|
// <o.25> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
|
||||||
|
// <o.21> DBG_CAN2_STOP <i> Debug CAN2 stopped when core is halted
|
||||||
|
// <o.20> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
|
||||||
|
// <o.19> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
|
||||||
|
// <o.18> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
|
||||||
|
// <o.17> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
|
||||||
|
// <o.16> DBG_I2C2_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
|
||||||
|
// <o.15> DBG_I2C1_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
|
||||||
|
// <o.14> DBG_CAN1_STOP <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <o.13> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
|
||||||
|
// <o.12> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
|
||||||
|
// <o.11> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
|
||||||
|
// <o.10> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
|
||||||
|
// <o.9> DBG_WWDG_STOP <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <o.8> DBG_IWDG_STOP <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <o.2> DBG_STANDBY <i> Debug standby mode
|
||||||
|
// <o.1> DBG_STOP <i> Debug stop mode
|
||||||
|
// <o.0> DBG_SLEEP <i> Debug sleep mode
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
// <h> Debug MCU Configuration
|
||||||
|
// <o0.0> DBG_SLEEP
|
||||||
|
// <i> Debug Sleep Mode
|
||||||
|
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||||
|
// <o0.1> DBG_STOP
|
||||||
|
// <i> Debug Stop Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.2> DBG_STANDBY
|
||||||
|
// <i> Debug Standby Mode
|
||||||
|
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||||
|
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||||
|
// <o0.8> DBG_IWDG_STOP
|
||||||
|
// <i> Debug independent watchdog stopped when core is halted
|
||||||
|
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.9> DBG_WWDG_STOP
|
||||||
|
// <i> Debug window watchdog stopped when core is halted
|
||||||
|
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||||
|
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||||
|
// <o0.10> DBG_TIM1_STOP
|
||||||
|
// <i> Timer 1 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.11> DBG_TIM2_STOP
|
||||||
|
// <i> Timer 2 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.12> DBG_TIM3_STOP
|
||||||
|
// <i> Timer 3 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.13> DBG_TIM4_STOP
|
||||||
|
// <i> Timer 4 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||||
|
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||||
|
// <o0.14> DBG_CAN1_STOP
|
||||||
|
// <i> Debug CAN1 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN1 receive registers are frozen
|
||||||
|
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||||
|
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: The SMBUS timeout is frozen
|
||||||
|
// <o0.17> DBG_TIM8_STOP
|
||||||
|
// <i> Timer 8 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.18> DBG_TIM5_STOP
|
||||||
|
// <i> Timer 5 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.19> DBG_TIM6_STOP
|
||||||
|
// <i> Timer 6 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.20> DBG_TIM7_STOP
|
||||||
|
// <i> Timer 7 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.21> DBG_CAN2_STOP
|
||||||
|
// <i> Debug CAN2 stopped when Core is halted
|
||||||
|
// <i> 0: Same behavior as in normal mode
|
||||||
|
// <i> 1: CAN2 receive registers are frozen
|
||||||
|
// <o0.25> DBG_TIM12_STOP
|
||||||
|
// <i> Timer 12 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.26> DBG_TIM13_STOP
|
||||||
|
// <i> Timer 13 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.27> DBG_TIM14_STOP
|
||||||
|
// <i> Timer 14 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.28> DBG_TIM9_STOP
|
||||||
|
// <i> Timer 9 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.29> DBG_TIM10_STOP
|
||||||
|
// <i> Timer 10 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// <o0.30> DBG_TIM11_STOP
|
||||||
|
// <i> Timer 11 counter stopped when core is halted
|
||||||
|
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||||
|
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||||
|
// </h>
|
||||||
|
DbgMCU_CR = 0x00000007;
|
||||||
|
// <<< end of configuration section >>>
|
||||||
20
STM32/STM32-F103ZET6/MDK-ARM/RTE/_1.2/RTE_Components.h
Normal file
20
STM32/STM32-F103ZET6/MDK-ARM/RTE/_1.2/RTE_Components.h
Normal file
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: '1.2'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
20
STM32/STM32-F103ZET6/MDK-ARM/RTE/_11/RTE_Components.h
Normal file
20
STM32/STM32-F103ZET6/MDK-ARM/RTE/_11/RTE_Components.h
Normal file
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: '11'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
20
STM32/STM32-F103ZET6/MDK-ARM/RTE/_11111/RTE_Components.h
Normal file
20
STM32/STM32-F103ZET6/MDK-ARM/RTE/_11111/RTE_Components.h
Normal file
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: '11111'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_1in02d_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_1in54_V2_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_1in54_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_1in54b_V2_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_1in54b_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_1in54c_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_1in64g_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_2in13_V2_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_2in13_V3_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_2in13_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_2in13b_V3_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_2in13b_V4_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_2in13bc_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_2in13d_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_2in36g_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_2in66_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_2in66b_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_2in7_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_2in7b_V2_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_2in7b_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_2in9_V2_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_2in9_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_2in9b_V3_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_2in9bc_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_2in9d_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_3in0g_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_3in52_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_3in7_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_4in01f_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_4in2_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_4in2b_V2_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_4in2bc_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_4in37g_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_5in65f_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_5in83_V2_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_5in83_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_5in83b_V2_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_5in83bc_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_7in3g_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_7in5_HD_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_7in5_V2_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_7in5_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Auto generated Run-Time-Environment Component Configuration File
|
||||||
|
* *** Do not modify ! ***
|
||||||
|
*
|
||||||
|
* Project: 'epd-demo'
|
||||||
|
* Target: 'EPD_7in5b_HD_test'
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RTE_COMPONENTS_H
|
||||||
|
#define RTE_COMPONENTS_H
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the Device Header File:
|
||||||
|
*/
|
||||||
|
#define CMSIS_device_header "stm32f10x.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* RTE_COMPONENTS_H */
|
||||||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Add table
Add a link
Reference in a new issue