STM32 provides a new compilation mode that greatly reduces the initial compilation time and is easier to operate.

STM32/ReadMe.txt

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+中文：
+简单使用：
+打开工程后点击编译栏的下拉框，选择对应屏幕的目标，然后点击编译。
+
+English：
+Easy to use:
+After opening the project, click the drop-down box in the Compile bar, select the target of the corresponding screen, and then click Compile.

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/1.2_STM32F103ZE.dbgconf

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+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/1.2_STM32F103ZG.dbgconf

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+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/1.2_STM32F105RB.dbgconf

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+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/11111_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/11_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_1in02d_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_1in54_V2_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_1in54_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_1in54b_V2_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_1in54b_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_1in54c_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_1in64g_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in13_V2_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in13_V3_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in13_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in13b_V3_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in13b_V4_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in13bc_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in13d_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in36g_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in66_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in66b_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in7_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in7b_V2_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in7b_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in9_V2_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in9_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in9b_V3_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in9bc_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in9d_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_3in0g_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_3in52_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_3in52_test_STM32F103ZE_1.0.0.dbgconf

@@ -0,0 +1,36 @@
+// File: STM32F101_102_103_105_107.dbgconf
+// Version: 1.0.0
+// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008)
+//                STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Debug MCU configuration register (DBGMCU_CR)
+//                                   <i> Reserved bits must be kept at reset value
+//   <o.30> DBG_TIM11_STOP           <i> TIM11 counter stopped when core is halted
+//   <o.29> DBG_TIM10_STOP           <i> TIM10 counter stopped when core is halted
+//   <o.28> DBG_TIM9_STOP            <i> TIM9 counter stopped when core is halted
+//   <o.27> DBG_TIM14_STOP           <i> TIM14 counter stopped when core is halted
+//   <o.26> DBG_TIM13_STOP           <i> TIM13 counter stopped when core is halted
+//   <o.25> DBG_TIM12_STOP           <i> TIM12 counter stopped when core is halted
+//   <o.21> DBG_CAN2_STOP            <i> Debug CAN2 stopped when core is halted
+//   <o.20> DBG_TIM7_STOP            <i> TIM7 counter stopped when core is halted
+//   <o.19> DBG_TIM6_STOP            <i> TIM6 counter stopped when core is halted
+//   <o.18> DBG_TIM5_STOP            <i> TIM5 counter stopped when core is halted
+//   <o.17> DBG_TIM8_STOP            <i> TIM8 counter stopped when core is halted
+//   <o.16> DBG_I2C2_SMBUS_TIMEOUT   <i> SMBUS timeout mode stopped when core is halted
+//   <o.15> DBG_I2C1_SMBUS_TIMEOUT   <i> SMBUS timeout mode stopped when core is halted
+//   <o.14> DBG_CAN1_STOP            <i> Debug CAN1 stopped when Core is halted
+//   <o.13> DBG_TIM4_STOP            <i> TIM4 counter stopped when core is halted
+//   <o.12> DBG_TIM3_STOP            <i> TIM3 counter stopped when core is halted
+//   <o.11> DBG_TIM2_STOP            <i> TIM2 counter stopped when core is halted
+//   <o.10> DBG_TIM1_STOP            <i> TIM1 counter stopped when core is halted
+//   <o.9>  DBG_WWDG_STOP            <i> Debug window watchdog stopped when core is halted
+//   <o.8>  DBG_IWDG_STOP            <i> Debug independent watchdog stopped when core is halted
+//   <o.2>  DBG_STANDBY              <i> Debug standby mode
+//   <o.1>  DBG_STOP                 <i> Debug stop mode
+//   <o.0>  DBG_SLEEP                <i> Debug sleep mode
+// </h>
+DbgMCU_CR = 0x00000007;
+
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_3in7_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_4in01f_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_4in2_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_4in2b_V2_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_4in2bc_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_4in37g_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_5in65f_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_5in83_V2_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_5in83_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_5in83b_V2_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_5in83bc_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_7in3g_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_7in5_HD_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_7in5_V2_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_7in5_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_7in5b_HD_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_7in5b_V2_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_7in5bc_test_STM32F103ZE.dbgconf

@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>

STM32/STM32-F103ZET6/MDK-ARM/RTE/_1.2/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  '1.2' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_11/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  '11' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_11111/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  '11111' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_1in02d_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_1in02d_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_1in54_V2_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_1in54_V2_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_1in54_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_1in54_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_1in54b_V2_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_1in54b_V2_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_1in54b_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_1in54b_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_1in54c_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_1in54c_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_1in64g_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_1in64g_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in13_V2_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_2in13_V2_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in13_V3_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_2in13_V3_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in13_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_2in13_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in13b_V3_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_2in13b_V3_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in13b_V4_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_2in13b_V4_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in13bc_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_2in13bc_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in13d_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_2in13d_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in36g_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_2in36g_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in66_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_2in66_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in66b_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_2in66b_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in7_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_2in7_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in7b_V2_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_2in7b_V2_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in7b_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_2in7b_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in9_V2_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_2in9_V2_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in9_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_2in9_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in9b_V3_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_2in9b_V3_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in9bc_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_2in9bc_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in9d_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_2in9d_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_3in0g_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_3in0g_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_3in52_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_3in52_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_3in7_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_3in7_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_4in01f_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_4in01f_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_4in2_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_4in2_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_4in2b_V2_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_4in2b_V2_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_4in2bc_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_4in2bc_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_4in37g_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_4in37g_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_5in65f_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_5in65f_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_5in83_V2_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_5in83_V2_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_5in83_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_5in83_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_5in83b_V2_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_5in83b_V2_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_5in83bc_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_5in83bc_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_7in3g_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_7in3g_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_7in5_HD_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_7in5_HD_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_7in5_V2_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_7in5_V2_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_7in5_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_7in5_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_7in5b_HD_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_7in5b_HD_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_7in5b_V2_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_7in5b_V2_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */

STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_7in5bc_test/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'epd-demo' 
+ * Target:  'EPD_7in5bc_test' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+
+#endif /* RTE_COMPONENTS_H */