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.../User/Examples/EPD_2in13_V2_test.c | 2 +- .../User/Examples/EPD_2in13_V3_test.c | 2 +- .../User/Examples/EPD_2in13_test.c | 2 +- .../User/Examples/EPD_2in13b_V3_test.c | 2 +- .../User/Examples/EPD_2in13b_V4_test.c | 2 +- .../User/Examples/EPD_2in13bc_test.c | 2 +- .../User/Examples/EPD_2in13d_test.c | 2 +- .../User/Examples/EPD_2in36g_test.c | 2 +- .../User/Examples/EPD_2in66_test.c | 2 +- .../User/Examples/EPD_2in66b_test.c | 2 +- .../User/Examples/EPD_2in7_test.c | 2 +- .../User/Examples/EPD_2in7b_V2_test.c | 2 +- .../User/Examples/EPD_2in7b_test.c | 2 +- .../User/Examples/EPD_2in9_V2_test.c | 2 +- .../User/Examples/EPD_2in9_test.c | 2 +- .../User/Examples/EPD_2in9b_V3_test.c | 2 +- .../User/Examples/EPD_2in9bc_test.c | 2 +- .../User/Examples/EPD_2in9d_test.c | 2 +- .../User/Examples/EPD_3in0g_test.c | 2 +- .../User/Examples/EPD_3in52_test.c | 6 +- .../User/Examples/EPD_3in7_test.c | 2 +- .../User/Examples/EPD_4in01f_test.c | 2 +- .../User/Examples/EPD_4in2_test.c | 22 +- .../User/Examples/EPD_4in2b_V2_test.c | 2 +- .../User/Examples/EPD_4in2bc_test.c | 2 +- .../User/Examples/EPD_4in37g_test.c | 2 +- .../User/Examples/EPD_5in65f_test.c | 2 +- .../User/Examples/EPD_5in83_V2_test.c | 2 +- .../User/Examples/EPD_5in83_test.c | 2 +- .../User/Examples/EPD_5in83b_V2_test.c | 2 +- .../User/Examples/EPD_5in83bc_test.c | 2 +- .../User/Examples/EPD_7in3g_test.c | 2 +- .../User/Examples/EPD_7in5_HD_test.c | 20 +- .../User/Examples/EPD_7in5_V2_test.c | 18 +- .../User/Examples/EPD_7in5_test.c | 2 +- .../User/Examples/EPD_7in5b_HD_test.c | 12 +- .../User/Examples/EPD_7in5b_V2_test.c | 2 +- .../User/Examples/EPD_7in5bc_test.c | 2 +- STM32/STM32-F103ZET6/User/Examples/EPD_Test.h | 58 +- .../STM32-F103ZET6/User/Examples/ImageData2.c | 7 +- .../STM32-F103ZET6/User/e-Paper/EPD_1in64g.c | 8 - .../STM32-F103ZET6/User/e-Paper/EPD_2in36g.c | 8 - STM32/STM32-F103ZET6/User/e-Paper/EPD_2in7.c | 30 +- .../STM32-F103ZET6/User/e-Paper/EPD_2in9bc.c | 4 +- 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"__cpp_inheriting_constructors=201511", + "__BUILTIN_AVR_ULLKBITS=1", + "__INT_LEAST64_MAX__=0x7fffffffffffffffLL", + "__DEC64_MIN__=1E-383DD", + "__WINT_TYPE__=int", + "__UINT_LEAST32_TYPE__=long unsigned int", + "__SIZEOF_SHORT__=2", + "__ULLFRACT_IBIT__=0", + "__LDBL_MIN_EXP__=(-125)", + "__UDA_IBIT__=32", + "__WINT_WIDTH__=16", + "__INT_LEAST8_MAX__=0x7f", + "__LFRACT_FBIT__=31", + "__LDBL_MAX_10_EXP__=38", + "__ATOMIC_RELAXED=0", + "__DBL_EPSILON__=double(1.19209290e-7L)", + "__BUILTIN_AVR_BITSUK=1", + "__BUILTIN_AVR_BITSUR=1", + "__UINT8_C(c)=c", + "__INT_LEAST32_TYPE__=long int", + "__BUILTIN_AVR_URBITS=1", + "__SIZEOF_WCHAR_T__=2", + "__LLFRACT_MAX__=0X7FFFFFFFFFFFFFFFP-63LLR", + "__TQ_FBIT__=127", + "__INT_FAST8_TYPE__=signed char", + "__ULLACCUM_EPSILON__=0x1P-48ULLK", + "__BUILTIN_AVR_ROUNDK=1", + "__BUILTIN_AVR_ROUNDR=1", + "__UHQ_IBIT__=0", + "__LLACCUM_IBIT__=16", + "__FLT32_EPSILON__=1.19209290e-7F32", + "__DBL_DECIMAL_DIG__=9", + "__STDC_UTF_32__=1", + "__INT_FAST8_WIDTH__=8", + "__DEC_EVAL_METHOD__=2", + "__TA_FBIT__=47", + "__UDQ_IBIT__=0", + "__ORDER_BIG_ENDIAN__=4321", + "__cpp_runtime_arrays=198712", + "__WITH_AVRLIBC__=1", + "__UINT64_TYPE__=long long unsigned int", + "__ACCUM_EPSILON__=0x1P-15K", + "__UINT32_C(c)=c ## UL", + "__BUILTIN_AVR_COUNTLSUHK=1", + "__INTMAX_MAX__=0x7fffffffffffffffLL", + "__cpp_alias_templates=200704", + "__BUILTIN_AVR_COUNTLSUHR=1", + "__BYTE_ORDER__=__ORDER_LITTLE_ENDIAN__", + "__FLT_DENORM_MIN__=1.40129846e-45F", + "__LLFRACT_IBIT__=0", + "__INT8_MAX__=0x7f", + "__LONG_WIDTH__=32", + "__UINT_FAST32_TYPE__=long unsigned int", + "__CHAR32_TYPE__=long unsigned int", + "__BUILTIN_AVR_COUNTLSULK=1", + "__BUILTIN_AVR_COUNTLSULR=1", + "__FLT_MAX__=3.40282347e+38F", + "__cpp_constexpr=201304", + "__USACCUM_FBIT__=8", + "__BUILTIN_AVR_COUNTLSFX=1", + "__INT32_TYPE__=long int", + "__SIZEOF_DOUBLE__=4", + "__FLT_MIN_10_EXP__=(-37)", + "__UFRACT_EPSILON__=0x1P-16UR", + "__INT_LEAST32_WIDTH__=32", + "__BUILTIN_AVR_COUNTLSHK=1", + "__BUILTIN_AVR_COUNTLSHR=1", + "__INTMAX_TYPE__=long long int", + "__BUILTIN_AVR_ABSLLK=1", + "__BUILTIN_AVR_ABSLLR=1", + "__DEC128_MAX_EXP__=6145", + "__AVR_HAVE_16BIT_SP__=1", + "__ATOMIC_CONSUME=1", + "__GNUC_MINOR__=3", + "__INT_FAST16_WIDTH__=16", + "__UINTMAX_MAX__=0xffffffffffffffffULL", + "__DEC32_MANT_DIG__=7", + "__HA_FBIT__=7", + "__BUILTIN_AVR_COUNTLSLK=1", + "__BUILTIN_AVR_COUNTLSLR=1", + "__BUILTIN_AVR_CLI=1", + "__DBL_MAX_10_EXP__=38", + "__LDBL_DENORM_MIN__=1.40129846e-45L", + "__INT16_C(c)=c", + "__cpp_generic_lambdas=201304", + "__STDC__=1", + "__PTRDIFF_TYPE__=int", + "__LLFRACT_MIN__=(-0.5LLR-0.5LLR)", + "__BUILTIN_AVR_LRBITS=1", + "__ATOMIC_SEQ_CST=5", + "__DA_FBIT__=31", + "__UINT32_TYPE__=long unsigned int", + "__BUILTIN_AVR_ROUNDLLK=1", + "__UINTPTR_TYPE__=unsigned int", + "__BUILTIN_AVR_ROUNDLLR=1", + "__USA_IBIT__=16", + "__BUILTIN_AVR_ULRBITS=1", + "__DEC64_SUBNORMAL_MIN__=0.000000000000001E-383DD", + "__DEC128_MANT_DIG__=34", + "__LDBL_MIN_10_EXP__=(-37)", + "__BUILTIN_AVR_COUNTLSUK=1", + "__BUILTIN_AVR_COUNTLSUR=1", + "__SIZEOF_LONG_LONG__=8", + "__ULACCUM_EPSILON__=0x1P-32ULK", + "__cpp_user_defined_literals=200809", + "__SACCUM_IBIT__=8", + "__GCC_ATOMIC_LLONG_LOCK_FREE=1", + "__LDBL_DIG__=6", + "__FLT_DECIMAL_DIG__=9", + "__UINT_FAST16_MAX__=0xffffU", + "__GCC_ATOMIC_SHORT_LOCK_FREE=1", + "__BUILTIN_AVR_ABSHK=1", + "__BUILTIN_AVR_FLASH_SEGMENT=1", + "__INT_LEAST64_WIDTH__=64", + "__ULLFRACT_MAX__=0XFFFFFFFFFFFFFFFFP-64ULLR", + "__UINT_FAST8_TYPE__=unsigned char", + "__USFRACT_EPSILON__=0x1P-8UHR", + "__ULACCUM_FBIT__=32", + "__QQ_IBIT__=0", + "__cpp_init_captures=201304", + "__ATOMIC_ACQ_REL=4", + "__ATOMIC_RELEASE=3", + "__BUILTIN_AVR_FMUL=1", + "USBCON" + ] + } + ] +} \ No newline at end of file diff --git a/STM32/ReadMe.txt b/STM32/ReadMe.txt new file mode 100644 index 0000000..2fe1f2e --- /dev/null +++ b/STM32/ReadMe.txt @@ -0,0 +1,7 @@ +中文: +简单使用: +打开工程后点击编译栏的下拉框,选择对应屏幕的目标,然后点击编译。 + +English: +Easy to use: +After opening the project, click the drop-down box in the Compile bar, select the target of the corresponding screen, and then click Compile. \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/1.2_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/1.2_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/1.2_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/1.2_STM32F103ZG.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/1.2_STM32F103ZG.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/1.2_STM32F103ZG.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/1.2_STM32F105RB.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/1.2_STM32F105RB.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/1.2_STM32F105RB.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/11111_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/11111_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/11111_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/11_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/11_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/11_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_1in02d_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_1in02d_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_1in02d_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_1in54_V2_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_1in54_V2_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_1in54_V2_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_1in54_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_1in54_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_1in54_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_1in54b_V2_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_1in54b_V2_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_1in54b_V2_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_1in54b_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_1in54b_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_1in54b_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_1in54c_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_1in54c_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_1in54c_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_1in64g_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_1in64g_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_1in64g_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in13_V2_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in13_V2_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in13_V2_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in13_V3_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in13_V3_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in13_V3_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in13_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in13_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in13_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in13b_V3_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in13b_V3_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in13b_V3_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in13b_V4_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in13b_V4_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in13b_V4_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in13bc_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in13bc_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in13bc_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in13d_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in13d_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in13d_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in36g_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in36g_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in36g_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in66_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in66_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in66_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in66b_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in66b_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in66b_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in7_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in7_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in7_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in7b_V2_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in7b_V2_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in7b_V2_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in7b_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in7b_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in7b_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in9_V2_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in9_V2_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in9_V2_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in9_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in9_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in9_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in9b_V3_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in9b_V3_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in9b_V3_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in9bc_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in9bc_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in9bc_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in9d_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in9d_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_2in9d_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_3in0g_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_3in0g_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_3in0g_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_3in52_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_3in52_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_3in52_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_3in52_test_STM32F103ZE_1.0.0.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_3in52_test_STM32F103ZE_1.0.0.dbgconf new file mode 100644 index 0000000..66e10b6 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_3in52_test_STM32F103ZE_1.0.0.dbgconf @@ -0,0 +1,36 @@ +// File: STM32F101_102_103_105_107.dbgconf +// Version: 1.0.0 +// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008) +// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets + +// <<< Use Configuration Wizard in Context Menu >>> + +// Debug MCU configuration register (DBGMCU_CR) +// Reserved bits must be kept at reset value +// DBG_TIM11_STOP TIM11 counter stopped when core is halted +// DBG_TIM10_STOP TIM10 counter stopped when core is halted +// DBG_TIM9_STOP TIM9 counter stopped when core is halted +// DBG_TIM14_STOP TIM14 counter stopped when core is halted +// DBG_TIM13_STOP TIM13 counter stopped when core is halted +// DBG_TIM12_STOP TIM12 counter stopped when core is halted +// DBG_CAN2_STOP Debug CAN2 stopped when core is halted +// DBG_TIM7_STOP TIM7 counter stopped when core is halted +// DBG_TIM6_STOP TIM6 counter stopped when core is halted +// DBG_TIM5_STOP TIM5 counter stopped when core is halted +// DBG_TIM8_STOP TIM8 counter stopped when core is halted +// DBG_I2C2_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_CAN1_STOP Debug CAN1 stopped when Core is halted +// DBG_TIM4_STOP TIM4 counter stopped when core is halted +// DBG_TIM3_STOP TIM3 counter stopped when core is halted +// DBG_TIM2_STOP TIM2 counter stopped when core is halted +// DBG_TIM1_STOP TIM1 counter stopped when core is halted +// DBG_WWDG_STOP Debug window watchdog stopped when core is halted +// DBG_IWDG_STOP Debug independent watchdog stopped when core is halted +// DBG_STANDBY Debug standby mode +// DBG_STOP Debug stop mode +// DBG_SLEEP Debug sleep mode +// +DbgMCU_CR = 0x00000007; + +// <<< end of configuration section >>> diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_3in7_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_3in7_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_3in7_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_4in01f_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_4in01f_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_4in01f_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_4in2_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_4in2_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_4in2_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_4in2b_V2_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_4in2b_V2_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_4in2b_V2_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_4in2bc_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_4in2bc_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_4in2bc_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_4in37g_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_4in37g_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_4in37g_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_5in65f_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_5in65f_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_5in65f_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_5in83_V2_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_5in83_V2_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_5in83_V2_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_5in83_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_5in83_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_5in83_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_5in83b_V2_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_5in83b_V2_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_5in83b_V2_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_5in83bc_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_5in83bc_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_5in83bc_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_7in3g_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_7in3g_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_7in3g_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_7in5_HD_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_7in5_HD_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_7in5_HD_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_7in5_V2_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_7in5_V2_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_7in5_V2_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_7in5_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_7in5_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_7in5_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_7in5b_HD_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_7in5b_HD_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_7in5b_HD_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_7in5b_V2_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_7in5b_V2_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_7in5b_V2_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_7in5bc_test_STM32F103ZE.dbgconf b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_7in5bc_test_STM32F103ZE.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/DebugConfig/EPD_7in5bc_test_STM32F103ZE.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_1.2/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_1.2/RTE_Components.h new file mode 100644 index 0000000..41ebf95 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_1.2/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: '1.2' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_11/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_11/RTE_Components.h new file mode 100644 index 0000000..04dd79b --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_11/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: '11' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_11111/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_11111/RTE_Components.h new file mode 100644 index 0000000..318be09 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_11111/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: '11111' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_1in02d_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_1in02d_test/RTE_Components.h new file mode 100644 index 0000000..3675825 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_1in02d_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_1in02d_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_1in54_V2_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_1in54_V2_test/RTE_Components.h new file mode 100644 index 0000000..bd63b39 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_1in54_V2_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_1in54_V2_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_1in54_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_1in54_test/RTE_Components.h new file mode 100644 index 0000000..f791099 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_1in54_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_1in54_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_1in54b_V2_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_1in54b_V2_test/RTE_Components.h new file mode 100644 index 0000000..784a156 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_1in54b_V2_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_1in54b_V2_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_1in54b_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_1in54b_test/RTE_Components.h new file mode 100644 index 0000000..16e0bc9 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_1in54b_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_1in54b_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_1in54c_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_1in54c_test/RTE_Components.h new file mode 100644 index 0000000..00e1330 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_1in54c_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_1in54c_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_1in64g_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_1in64g_test/RTE_Components.h new file mode 100644 index 0000000..5c3b982 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_1in64g_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_1in64g_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in13_V2_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in13_V2_test/RTE_Components.h new file mode 100644 index 0000000..d368419 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in13_V2_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_2in13_V2_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in13_V3_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in13_V3_test/RTE_Components.h new file mode 100644 index 0000000..9189994 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in13_V3_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_2in13_V3_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in13_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in13_test/RTE_Components.h new file mode 100644 index 0000000..95e6d42 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in13_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_2in13_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in13b_V3_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in13b_V3_test/RTE_Components.h new file mode 100644 index 0000000..47692c2 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in13b_V3_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_2in13b_V3_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in13b_V4_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in13b_V4_test/RTE_Components.h new file mode 100644 index 0000000..9656d26 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in13b_V4_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_2in13b_V4_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in13bc_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in13bc_test/RTE_Components.h new file mode 100644 index 0000000..35bdc01 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in13bc_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_2in13bc_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in13d_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in13d_test/RTE_Components.h new file mode 100644 index 0000000..e9f96bb --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in13d_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_2in13d_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in36g_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in36g_test/RTE_Components.h new file mode 100644 index 0000000..0f28d21 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in36g_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_2in36g_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in66_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in66_test/RTE_Components.h new file mode 100644 index 0000000..9503ed1 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in66_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_2in66_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in66b_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in66b_test/RTE_Components.h new file mode 100644 index 0000000..b2ad496 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in66b_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_2in66b_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in7_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in7_test/RTE_Components.h new file mode 100644 index 0000000..916bd57 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in7_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_2in7_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in7b_V2_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in7b_V2_test/RTE_Components.h new file mode 100644 index 0000000..30eb65a --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in7b_V2_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_2in7b_V2_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in7b_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in7b_test/RTE_Components.h new file mode 100644 index 0000000..2d71e6c --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in7b_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_2in7b_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in9_V2_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in9_V2_test/RTE_Components.h new file mode 100644 index 0000000..cacfb16 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in9_V2_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_2in9_V2_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in9_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in9_test/RTE_Components.h new file mode 100644 index 0000000..308a625 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in9_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_2in9_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in9b_V3_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in9b_V3_test/RTE_Components.h new file mode 100644 index 0000000..f6bc54c --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in9b_V3_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_2in9b_V3_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in9bc_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in9bc_test/RTE_Components.h new file mode 100644 index 0000000..a0dfaae --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in9bc_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_2in9bc_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in9d_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in9d_test/RTE_Components.h new file mode 100644 index 0000000..db439cb --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_2in9d_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_2in9d_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_3in0g_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_3in0g_test/RTE_Components.h new file mode 100644 index 0000000..b24cc45 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_3in0g_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_3in0g_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_3in52_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_3in52_test/RTE_Components.h new file mode 100644 index 0000000..89b4c2f --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_3in52_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_3in52_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_3in7_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_3in7_test/RTE_Components.h new file mode 100644 index 0000000..cd0a1c5 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_3in7_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_3in7_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_4in01f_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_4in01f_test/RTE_Components.h new file mode 100644 index 0000000..3cbd0ed --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_4in01f_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_4in01f_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_4in2_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_4in2_test/RTE_Components.h new file mode 100644 index 0000000..534ef4c --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_4in2_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_4in2_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_4in2b_V2_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_4in2b_V2_test/RTE_Components.h new file mode 100644 index 0000000..bb7999b --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_4in2b_V2_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_4in2b_V2_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_4in2bc_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_4in2bc_test/RTE_Components.h new file mode 100644 index 0000000..c29c99b --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_4in2bc_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_4in2bc_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_4in37g_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_4in37g_test/RTE_Components.h new file mode 100644 index 0000000..4a96346 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_4in37g_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_4in37g_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_5in65f_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_5in65f_test/RTE_Components.h new file mode 100644 index 0000000..b3faf07 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_5in65f_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_5in65f_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_5in83_V2_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_5in83_V2_test/RTE_Components.h new file mode 100644 index 0000000..77137b6 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_5in83_V2_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_5in83_V2_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_5in83_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_5in83_test/RTE_Components.h new file mode 100644 index 0000000..11dba96 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_5in83_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_5in83_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_5in83b_V2_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_5in83b_V2_test/RTE_Components.h new file mode 100644 index 0000000..53463cd --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_5in83b_V2_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_5in83b_V2_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_5in83bc_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_5in83bc_test/RTE_Components.h new file mode 100644 index 0000000..51b87b7 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_5in83bc_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_5in83bc_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_7in3g_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_7in3g_test/RTE_Components.h new file mode 100644 index 0000000..0ceced9 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_7in3g_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_7in3g_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_7in5_HD_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_7in5_HD_test/RTE_Components.h new file mode 100644 index 0000000..3a65ff2 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_7in5_HD_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_7in5_HD_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_7in5_V2_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_7in5_V2_test/RTE_Components.h new file mode 100644 index 0000000..67892dd --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_7in5_V2_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_7in5_V2_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_7in5_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_7in5_test/RTE_Components.h new file mode 100644 index 0000000..b980488 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_7in5_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_7in5_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_7in5b_HD_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_7in5b_HD_test/RTE_Components.h new file mode 100644 index 0000000..d9d4c01 --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_7in5b_HD_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_7in5b_HD_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_7in5b_V2_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_7in5b_V2_test/RTE_Components.h new file mode 100644 index 0000000..7125bde --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_7in5b_V2_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_7in5b_V2_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_7in5bc_test/RTE_Components.h b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_7in5bc_test/RTE_Components.h new file mode 100644 index 0000000..c2bb2ca --- /dev/null +++ b/STM32/STM32-F103ZET6/MDK-ARM/RTE/_EPD_7in5bc_test/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'epd-demo' + * Target: 'EPD_7in5bc_test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/STM32/STM32-F103ZET6/MDK-ARM/epd-demo.uvguix.liuyujian b/STM32/STM32-F103ZET6/MDK-ARM/epd-demo.uvguix.liuyujian index 729593a..ac200d6 100644 --- a/STM32/STM32-F103ZET6/MDK-ARM/epd-demo.uvguix.liuyujian +++ b/STM32/STM32-F103ZET6/MDK-ARM/epd-demo.uvguix.liuyujian @@ -11,7 +11,7 @@ 38003 Registers - 188 122 + 188 116 346 @@ -89,8 +89,8 @@ 2 3 - -32000 - -32000 + -1 + -1 -1 @@ -106,8 +106,8 @@ 0 - 1270 - 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0 + 0 + 0 + ..\User\e-Paper\EPD_4in2b_V2.c + EPD_4in2b_V2.c + 0 + 0 + + + 4 + 87 1 0 0 @@ -1438,7 +11184,67 @@ 4 - 98 + 88 + 1 + 0 + 0 + 0 + ..\User\e-Paper\EPD_5in65f.c + EPD_5in65f.c + 0 + 0 + + + 4 + 89 + 1 + 0 + 0 + 0 + ..\User\e-Paper\EPD_5in83.c + EPD_5in83.c + 0 + 0 + + + 4 + 90 + 1 + 0 + 0 + 0 + ..\User\e-Paper\EPD_5in83_V2.c + EPD_5in83_V2.c + 0 + 0 + + + 4 + 91 + 1 + 0 + 0 + 0 + ..\User\e-Paper\EPD_5in83bc.c + EPD_5in83bc.c + 0 + 0 + + + 4 + 92 + 1 + 0 + 0 + 0 + ..\User\e-Paper\EPD_5in83b_V2.c + EPD_5in83b_V2.c + 0 + 0 + + + 4 + 93 1 0 0 @@ -1448,6 +11254,66 @@ 0 0 + + 4 + 94 + 1 + 0 + 0 + 0 + ..\User\e-Paper\EPD_7in5.c + EPD_7in5.c + 0 + 0 + + + 4 + 95 + 1 + 0 + 0 + 0 + ..\User\e-Paper\EPD_7in5_V2.c + EPD_7in5_V2.c + 0 + 0 + + + 4 + 96 + 1 + 0 + 0 + 0 + ..\User\e-Paper\EPD_7in5_HD.c + EPD_7in5_HD.c + 0 + 0 + + + 4 + 97 + 1 + 0 + 0 + 0 + ..\User\e-Paper\EPD_7in5bc.c + EPD_7in5bc.c + 0 + 0 + + + 4 + 98 + 1 + 0 + 0 + 0 + ..\User\e-Paper\EPD_7in5b_V2.c + EPD_7in5b_V2.c + 0 + 0 + 4 99 @@ -1455,8 +11321,8 @@ 0 0 0 - ..\User\e-Paper\EPD_2in36g.c - EPD_2in36g.c + ..\User\e-Paper\EPD_7in5b_HD.c + EPD_7in5b_HD.c 0 0 @@ -1834,6 +11700,14 @@ + + New Group + 0 + 0 + 0 + 0 + + ::CMSIS 0 diff --git a/STM32/STM32-F103ZET6/MDK-ARM/epd-demo.uvprojx b/STM32/STM32-F103ZET6/MDK-ARM/epd-demo.uvprojx index 019f806..d2ddbe5 100644 --- a/STM32/STM32-F103ZET6/MDK-ARM/epd-demo.uvprojx +++ b/STM32/STM32-F103ZET6/MDK-ARM/epd-demo.uvprojx @@ -16,7 +16,7 @@ STM32F103ZE STMicroelectronics - Keil.STM32F1xx_DFP.2.1.0 + Keil.STM32F1xx_DFP.2.3.0 http://www.keil.com/pack/ IRAM(0x20000000-0x2000FFFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3") @@ -184,7 +184,6 @@ 0 0 0 - 0 0 0 8 @@ -426,6 +425,75 @@ Examples + + + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + ImageData.c @@ -441,456 +509,5115 @@ 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EPD_2in13b_V4_test.c - 1 - ..\User\Examples\EPD_2in13b_V4_test.c - - - EPD_2in13bc_test.c - 1 - ..\User\Examples\EPD_2in13bc_test.c - - - EPD_2in13d_test.c - 1 - ..\User\Examples\EPD_2in13d_test.c - - - EPD_2in66_test.c - 1 - ..\User\Examples\EPD_2in66_test.c - - - EPD_2in66b_test.c - 1 - ..\User\Examples\EPD_2in66b_test.c - - - EPD_3in52_test.c - 1 - ..\User\Examples\EPD_3in52_test.c - - - EPD_3in7_test.c - 1 - ..\User\Examples\EPD_3in7_test.c - - - EPD_4in01f_test.c - 1 - ..\User\Examples\EPD_4in01f_test.c - - - EPD_4in2_test.c - 1 - ..\User\Examples\EPD_4in2_test.c - - - EPD_4in2bc_test.c - 1 - ..\User\Examples\EPD_4in2bc_test.c - - - EPD_4in2b_V2_test.c - 1 - ..\User\Examples\EPD_4in2b_V2_test.c - - - EPD_5in65f_test.c - 1 - ..\User\Examples\EPD_5in65f_test.c - - - EPD_5in83_test.c - 1 - ..\User\Examples\EPD_5in83_test.c - - - EPD_5in83_V2_test.c - 1 - ..\User\Examples\EPD_5in83_V2_test.c - - - EPD_5in83bc_test.c - 1 - ..\User\Examples\EPD_5in83bc_test.c - - - EPD_5in83b_V2_test.c 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11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + - EPD_4in37g_test.c + EPD_2in7b_test.c 1 - ..\User\Examples\EPD_4in37g_test.c + ..\User\Examples\EPD_2in7b_test.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + - EPD_7in3g_test.c + EPD_2in7b_V2_test.c 1 - ..\User\Examples\EPD_7in3g_test.c + ..\User\Examples\EPD_2in7b_V2_test.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + EPD_2in9_test.c + 1 + ..\User\Examples\EPD_2in9_test.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + EPD_2in9_V2_test.c + 1 + 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..\User\Readme_EN.txt + + + + + Drivers/CMSIS + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 0 + + + + 2 + 2 + 1 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + system_stm32f1xx.c + 1 + ../Src/system_stm32f1xx.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + + + Drivers/STM32F1xx_HAL_Driver + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 0 + + + + 2 + 2 + 1 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + stm32f1xx_hal_gpio_ex.c + 1 + ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + stm32f1xx_hal_spi.c + 1 + ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + stm32f1xx_hal.c + 1 + ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + stm32f1xx_hal_rcc.c + 1 + ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + stm32f1xx_hal_rcc_ex.c + 1 + ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + stm32f1xx_hal_gpio.c + 1 + ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + stm32f1xx_hal_dma.c + 1 + ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + stm32f1xx_hal_cortex.c + 1 + ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + stm32f1xx_hal_pwr.c + 1 + ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + stm32f1xx_hal_flash.c + 1 + ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + stm32f1xx_hal_flash_ex.c + 1 + ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + stm32f1xx_hal_exti.c + 1 + ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + stm32f1xx_hal_tim.c + 1 + ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + stm32f1xx_hal_tim_ex.c + 1 + ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + stm32f1xx_hal_uart.c + 1 + ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + + + New Group + ::CMSIS @@ -2023,9 +317769,54 @@ - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/STM32/STM32-F103ZET6/MDK-ARM/epd-demo/epd-demo.build_log.htm b/STM32/STM32-F103ZET6/MDK-ARM/epd-demo/epd-demo.build_log.htm deleted file mode 100644 index 3e1ca69..0000000 --- a/STM32/STM32-F103ZET6/MDK-ARM/epd-demo/epd-demo.build_log.htm +++ /dev/null @@ -1,204 +0,0 @@ - - -
-

Vision Build Log

-

Tool Versions:

-IDE-Version: Vision V5.26.2.0 -Copyright (C) 2018 ARM Ltd and ARM Germany GmbH. All rights reserved. -License Information: , , LIC=RC93N-YLJYL-JJH6S-LI3Z1-D1AV2-99PL8 - -Tool Versions: -Toolchain: MDK-ARM Plus Version: 5.26.2.0 -Toolchain Path: D:\KEIL\azwz\ARM\ARMCC\Bin -C Compiler: Armcc.exe V5.06 update 6 (build 750) -Assembler: Armasm.exe V5.06 update 6 (build 750) -Linker/Locator: ArmLink.exe V5.06 update 6 (build 750) -Library Manager: ArmAr.exe V5.06 update 6 (build 750) -Hex Converter: FromElf.exe V5.06 update 6 (build 750) -CPU DLL: SARMCM3.DLL V5.26.2.0 -Dialog DLL: DCM.DLL V1.17.2.0 -Target DLL: STLink\ST-LINKIII-KEIL_SWO.dll V3.0.5.0 -Dialog DLL: TCM.DLL V1.36.1.0 - -

Project:

-E:\Ŀ\e-Paper\Code\E-Paper_code\STM32\STM32-F103ZET6\MDK-ARM\epd-demo.uvprojx -Project File Date: 08/17/2022 - -

Output:

-*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'D:\KEIL\azwz\ARM\ARMCC\Bin' -Build target 'epd-demo' -assembling startup_stm32f103xe.s... -compiling gpio.c... -compiling usart.c... -compiling spi.c... -compiling main.c... -compiling stm32f1xx_it.c... -compiling ImageData2.c... -..\User\Examples\ImageData2.c(11767): warning: #1-D: last line of file ends without a newline - }; -..\User\Examples\ImageData2.c: 1 warning, 0 errors -compiling ImageData.c... -compiling stm32f1xx_hal_msp.c... -compiling EPD_1in54_V2_test.c... -compiling EPD_1in02_test.c... -compiling EPD_1in54_test.c... -compiling EPD_1in54b_test.c... -compiling EPD_2in7b_V2_test.c... -compiling EPD_1in54b_V2_test.c... -compiling EPD_2in7b_test.c... -compiling EPD_1in54c_test.c... -compiling EPD_2in7_test.c... -compiling EPD_2in9d_test.c... -compiling EPD_2in9bc_test.c... -compiling EPD_2in9b_V3_test.c... -compiling EPD_2in9_V2_test.c... -compiling EPD_2in9_test.c... -compiling EPD_2in13_test.c... -compiling EPD_2in13_V3_test.c... -compiling EPD_2in13_V2_test.c... -compiling EPD_2in13b_V3_test.c... -compiling EPD_2in13b_V4_test.c... -compiling EPD_3in52_test.c... -compiling EPD_2in13d_test.c... -compiling EPD_2in13bc_test.c... -compiling EPD_2in66_test.c... -compiling EPD_2in66b_test.c... -compiling EPD_3in7_test.c... -compiling EPD_4in2bc_test.c... -compiling EPD_4in2b_V2_test.c... -compiling EPD_4in2_test.c... -compiling EPD_4in01f_test.c... -compiling EPD_5in83_V2_test.c... -compiling EPD_5in83_test.c... -compiling EPD_5in65f_test.c... -compiling EPD_5in83b_V2_test.c... -compiling EPD_5in83bc_test.c... -compiling EPD_7in5b_V2_test.c... -compiling EPD_7in5_V2_test.c... -compiling EPD_7in5bc_test.c... -compiling EPD_7in5_test.c... -compiling EPD_7in5b_HD_test.c... -compiling EPD_7in5_HD_test.c... -compiling EPD_7in3g_test.c... -compiling EPD_3in0g_test.c... -compiling EPD_1in64g_test.c... -compiling EPD_4in37g_test.c... -compiling EPD_1in02d.c... -compiling EPD_1in54b.c... -compiling EPD_1in54.c... -compiling EPD_1in54_V2.c... -compiling EPD_2in36g_test.c... -compiling EPD_2in7.c... -compiling EPD_2in7b_V2.c... -compiling EPD_2in7b.c... -compiling EPD_1in54b_V2.c... -compiling EPD_1in54c.c... -compiling EPD_2in9.c... -compiling EPD_2in9d.c... -compiling EPD_2in9bc.c... -compiling EPD_2in9_V2.c... -compiling EPD_2in9b_V3.c... -compiling EPD_2in13_V2.c... -compiling EPD_2in13.c... -compiling EPD_2in13bc.c... -compiling EPD_2in13b_V3.c... -compiling EPD_2in13_V3.c... -compiling EPD_2in13b_V4.c... -compiling EPD_2in13d.c... -compiling EPD_2in66b.c... -compiling EPD_2in66.c... -compiling EPD_3in52.c... -compiling EPD_3in7.c... -compiling EPD_4in2.c... -..\User\e-Paper\EPD_4in2.c(612): warning: #550-D: variable "Height" was set but never used - UWORD Width, Height; -..\User\e-Paper\EPD_4in2.c: 1 warning, 0 errors -compiling EPD_4in2bc.c... -compiling EPD_4in2b_V2.c... -compiling EPD_4in01f.c... -compiling EPD_5in83bc.c... -compiling EPD_5in83b_V2.c... -compiling EPD_5in65f.c... -compiling EPD_5in83_V2.c... -compiling EPD_5in83.c... -compiling EPD_7in5_V2.c... -compiling EPD_7in5bc.c... -compiling EPD_7in5b_V2.c... -compiling EPD_7in5_HD.c... -compiling EPD_7in5.c... -compiling EPD_1in64g.c... -..\User\e-Paper\EPD_1in64g.c(86): warning: #177-D: function "EPD_1IN64G_ReadBusyL" was declared but never referenced - static void EPD_1IN64G_ReadBusyL(void) -..\User\e-Paper\EPD_1in64g.c: 1 warning, 0 errors -compiling EPD_7in5b_HD.c... -compiling EPD_3in0g.c... -..\User\e-Paper\EPD_3in0g.c(86): warning: #177-D: function "EPD_3IN0G_ReadBusyL" was declared but never referenced - static void EPD_3IN0G_ReadBusyL(void) -..\User\e-Paper\EPD_3in0g.c: 1 warning, 0 errors -compiling EPD_7in3g.c... -..\User\e-Paper\EPD_7in3g.c(86): warning: #177-D: function "EPD_7IN3G_ReadBusyL" was declared but never referenced - static void EPD_7IN3G_ReadBusyL(void) -..\User\e-Paper\EPD_7in3g.c: 1 warning, 0 errors -compiling EPD_4in37g.c... -..\User\e-Paper\EPD_4in37g.c(86): warning: #177-D: function "EPD_4IN37G_ReadBusyL" was declared but never referenced - static void EPD_4IN37G_ReadBusyL(void) -..\User\e-Paper\EPD_4in37g.c: 1 warning, 0 errors -compiling font8.c... -compiling font12.c... -compiling font12CN.c... -compiling font16.c... -compiling font20.c... -compiling font24.c... -compiling font24CN.c... -compiling DEV_Config.c... -compiling stm32f1xx_hal_gpio_ex.c... -compiling EPD_2in36g.c... -..\User\e-Paper\EPD_2in36g.c(86): warning: #177-D: function "EPD_2IN36G_ReadBusyL" was declared but never referenced - static void EPD_2IN36G_ReadBusyL(void) -..\User\e-Paper\EPD_2in36g.c: 1 warning, 0 errors -compiling system_stm32f1xx.c... -compiling GUI_Paint.c... -compiling stm32f1xx_hal.c... -compiling stm32f1xx_hal_gpio.c... -compiling stm32f1xx_hal_rcc_ex.c... -compiling stm32f1xx_hal_rcc.c... -compiling stm32f1xx_hal_spi.c... -compiling stm32f1xx_hal_flash.c... -compiling stm32f1xx_hal_cortex.c... -compiling stm32f1xx_hal_flash_ex.c... -compiling stm32f1xx_hal_pwr.c... -compiling stm32f1xx_hal_dma.c... -compiling stm32f1xx_hal_tim.c... -compiling stm32f1xx_hal_exti.c... -compiling stm32f1xx_hal_tim_ex.c... -compiling stm32f1xx_hal_uart.c... -linking... -Program Size: Code=24680 RO-data=21692 RW-data=56 ZI-data=53424 -FromELF: creating hex file... -"epd-demo\epd-demo.axf" - 0 Error(s), 7 Warning(s). - -

Software Packages used:

- -Package Vendor: ARM - http://www.keil.com/pack/ARM.CMSIS.5.9.0.pack - ARM.CMSIS.5.9.0 - CMSIS (Common Microcontroller Software Interface Standard) - * Component: CORE Version: 5.6.0 - -Package Vendor: Keil - http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.1.0.pack - Keil.STM32F1xx_DFP.2.1.0 - STMicroelectronics STM32F1 Series Device Support, Drivers and Examples - -

Collection of Component include folders:

- .\RTE\_epd-demo - D:\KEIL\azwz\ARM\PACK\ARM\CMSIS\5.9.0\CMSIS\Core\Include - D:\KEIL\azwz\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include - -

Collection of Component Files used:

- - * Component: ARM::CMSIS:CORE:5.6.0 -Build Time Elapsed: 00:00:56 -
- - diff --git a/STM32/STM32-F103ZET6/MDK-ARM/epd-demo/epd-demo.htm b/STM32/STM32-F103ZET6/MDK-ARM/epd-demo/epd-demo.htm deleted file mode 100644 index 482202b..0000000 --- a/STM32/STM32-F103ZET6/MDK-ARM/epd-demo/epd-demo.htm +++ /dev/null @@ -1,1825 +0,0 @@ - - -Static Call Graph - [epd-demo\epd-demo.axf] -
-

Static Call Graph for image epd-demo\epd-demo.axf


-

#<CALLGRAPH># ARM Linker, 5060750: Last Updated: Wed Aug 17 17:17:30 2022 -

-

Maximum Stack Usage = 760 bytes + Unknown(Cycles, Untraceable Function Pointers)

-Call chain for Maximum Stack Depth:

-main ⇒ EPD_2in36g_test ⇒ Paint_DrawNum ⇒ Paint_DrawString_EN ⇒ Paint_DrawChar ⇒ Paint_SetPixel ⇒ __2printf -

-

-Mutually Recursive functions -

  • ADC1_2_IRQHandler   ⇒   ADC1_2_IRQHandler
    -
  • Error_Handler   ⇒   Error_Handler
    -
  • MemManage_Handler   ⇒   MemManage_Handler
    -
  • BusFault_Handler   ⇒   BusFault_Handler
    -
  • UsageFault_Handler   ⇒   UsageFault_Handler
    - -

    -

    -Function Pointers -

      -
    • ADC1_2_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • ADC3_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • BusFault_Handler from stm32f1xx_it.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • CAN1_RX1_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • CAN1_SCE_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • DMA1_Channel1_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • DMA1_Channel2_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • DMA1_Channel3_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • DMA1_Channel4_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • DMA1_Channel5_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • DMA1_Channel6_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • DMA1_Channel7_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • DMA2_Channel1_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • DMA2_Channel2_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • DMA2_Channel3_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • DMA2_Channel4_5_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • DebugMon_Handler from stm32f1xx_it.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • EXTI0_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • EXTI15_10_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • EXTI1_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • EXTI2_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • EXTI3_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • EXTI4_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • EXTI9_5_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • FLASH_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • FSMC_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • HardFault_Handler from stm32f1xx_it.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • I2C1_ER_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • I2C1_EV_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • I2C2_ER_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • I2C2_EV_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • MemManage_Handler from stm32f1xx_it.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • NMI_Handler from stm32f1xx_it.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • PVD_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • PendSV_Handler from stm32f1xx_it.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • RCC_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • RTC_Alarm_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • RTC_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • Reset_Handler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • SDIO_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • SPI1_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • SPI2_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • SPI3_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • SPI_2linesRxISR_16BIT from stm32f1xx_hal_spi.o(.text) referenced from stm32f1xx_hal_spi.o(.text) -
    • SPI_2linesRxISR_8BIT from stm32f1xx_hal_spi.o(.text) referenced from stm32f1xx_hal_spi.o(.text) -
    • SPI_2linesTxISR_16BIT from stm32f1xx_hal_spi.o(.text) referenced from stm32f1xx_hal_spi.o(.text) -
    • SPI_2linesTxISR_8BIT from stm32f1xx_hal_spi.o(.text) referenced from stm32f1xx_hal_spi.o(.text) -
    • SPI_AbortRx_ISR from stm32f1xx_hal_spi.o(.text) referenced from stm32f1xx_hal_spi.o(.text) -
    • SPI_AbortTx_ISR from stm32f1xx_hal_spi.o(.text) referenced from stm32f1xx_hal_spi.o(.text) -
    • SPI_DMAAbortOnError from stm32f1xx_hal_spi.o(.text) referenced from stm32f1xx_hal_spi.o(.text) -
    • SPI_DMAError from stm32f1xx_hal_spi.o(.text) referenced 2 times from stm32f1xx_hal_spi.o(.text) -
    • SPI_DMAHalfReceiveCplt from stm32f1xx_hal_spi.o(.text) referenced 2 times from stm32f1xx_hal_spi.o(.text) -
    • SPI_DMAHalfTransmitCplt from stm32f1xx_hal_spi.o(.text) referenced from stm32f1xx_hal_spi.o(.text) -
    • SPI_DMAHalfTransmitReceiveCplt from stm32f1xx_hal_spi.o(.text) referenced from stm32f1xx_hal_spi.o(.text) -
    • SPI_DMAReceiveCplt from stm32f1xx_hal_spi.o(.text) referenced 2 times from stm32f1xx_hal_spi.o(.text) -
    • SPI_DMARxAbortCallback from stm32f1xx_hal_spi.o(.text) referenced from stm32f1xx_hal_spi.o(.text) -
    • SPI_DMATransmitCplt from stm32f1xx_hal_spi.o(.text) referenced from stm32f1xx_hal_spi.o(.text) -
    • SPI_DMATransmitReceiveCplt from stm32f1xx_hal_spi.o(.text) referenced from stm32f1xx_hal_spi.o(.text) -
    • SPI_DMATxAbortCallback from stm32f1xx_hal_spi.o(.text) referenced from stm32f1xx_hal_spi.o(.text) -
    • SPI_RxISR_16BIT from stm32f1xx_hal_spi.o(.text) referenced from stm32f1xx_hal_spi.o(.text) -
    • SPI_RxISR_8BIT from stm32f1xx_hal_spi.o(.text) referenced from stm32f1xx_hal_spi.o(.text) -
    • SPI_TxISR_16BIT from stm32f1xx_hal_spi.o(.text) referenced from stm32f1xx_hal_spi.o(.text) -
    • SPI_TxISR_8BIT from stm32f1xx_hal_spi.o(.text) referenced from stm32f1xx_hal_spi.o(.text) -
    • SVC_Handler from stm32f1xx_it.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • SysTick_Handler from stm32f1xx_it.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • SystemInit from system_stm32f1xx.o(.text) referenced from startup_stm32f103xe.o(.text) -
    • TAMPER_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • TIM1_BRK_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • TIM1_CC_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • TIM1_TRG_COM_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • TIM1_UP_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • TIM2_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • TIM3_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • TIM4_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • TIM5_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • TIM6_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • TIM7_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • TIM8_BRK_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • TIM8_CC_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • TIM8_TRG_COM_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • TIM8_UP_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • UART4_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • UART5_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • UART_DMAAbortOnError from stm32f1xx_hal_uart.o(.text) referenced from stm32f1xx_hal_uart.o(.text) -
    • UART_DMAError from stm32f1xx_hal_uart.o(.text) referenced from stm32f1xx_hal_uart.o(.text) -
    • UART_DMAReceiveCplt from stm32f1xx_hal_uart.o(.text) referenced from stm32f1xx_hal_uart.o(.text) -
    • UART_DMARxAbortCallback from stm32f1xx_hal_uart.o(.text) referenced from stm32f1xx_hal_uart.o(.text) -
    • UART_DMARxHalfCplt from stm32f1xx_hal_uart.o(.text) referenced from stm32f1xx_hal_uart.o(.text) -
    • UART_DMARxOnlyAbortCallback from stm32f1xx_hal_uart.o(.text) referenced from stm32f1xx_hal_uart.o(.text) -
    • UART_DMATransmitCplt from stm32f1xx_hal_uart.o(.text) referenced from stm32f1xx_hal_uart.o(.text) -
    • UART_DMATxAbortCallback from stm32f1xx_hal_uart.o(.text) referenced from stm32f1xx_hal_uart.o(.text) -
    • UART_DMATxHalfCplt from stm32f1xx_hal_uart.o(.text) referenced from stm32f1xx_hal_uart.o(.text) -
    • UART_DMATxOnlyAbortCallback from stm32f1xx_hal_uart.o(.text) referenced from stm32f1xx_hal_uart.o(.text) -
    • USART1_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • USART2_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • USART3_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • USBWakeUp_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • USB_HP_CAN1_TX_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • USB_LP_CAN1_RX0_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • UsageFault_Handler from stm32f1xx_it.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • WWDG_IRQHandler from startup_stm32f103xe.o(.text) referenced from startup_stm32f103xe.o(RESET) -
    • __main from entry.o(.ARM.Collect$$$$00000000) referenced from startup_stm32f103xe.o(.text) -
    • fputc from usart.o(.text) referenced from printf3.o(i.__0printf$3) -
    • main from main.o(.text) referenced from entry9a.o(.ARM.Collect$$$$0000000B) -
    -

    -

    -Global Symbols -

    -

    __main (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(.text) -
    -

    _main_stk (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001)) - -

    _main_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004)) -

    [Calls]

    • >>   __scatterload -
    - -

    __main_after_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004)) -

    [Called By]

    • >>   __scatterload -
    - -

    _main_clock (Thumb, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008)) - -

    _main_cpp_init (Thumb, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A)) - -

    _main_init (Thumb, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B)) - -

    __rt_final_cpp (Thumb, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000D)) - -

    __rt_final_exit (Thumb, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$0000000F)) - -

    Reset_Handler (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    ADC1_2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -

    [Calls]

    • >>   ADC1_2_IRQHandler -
    -
    [Called By]
    • >>   ADC1_2_IRQHandler -
    -
    [Address Reference Count : 1]
    • startup_stm32f103xe.o(RESET) -
    -

    ADC3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    CAN1_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    CAN1_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    DMA1_Channel1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    DMA1_Channel2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    DMA1_Channel3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    DMA1_Channel4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    DMA1_Channel5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    DMA1_Channel6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    DMA1_Channel7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    DMA2_Channel1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    DMA2_Channel2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    DMA2_Channel3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    DMA2_Channel4_5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    EXTI0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    EXTI15_10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    EXTI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    EXTI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    EXTI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    EXTI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    EXTI9_5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    FLASH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    FSMC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    I2C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    I2C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    I2C2_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    I2C2_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    PVD_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    RCC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    RTC_Alarm_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    RTC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    SDIO_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    SPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    SPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    SPI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    TAMPER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    TIM1_BRK_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    TIM1_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    TIM1_TRG_COM_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    TIM1_UP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    TIM2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    TIM3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    TIM4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    TIM5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    TIM6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    TIM7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    TIM8_BRK_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    TIM8_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    TIM8_TRG_COM_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    TIM8_UP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    UART4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    UART5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    USART1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    USART2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    USART3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    USBWakeUp_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    USB_HP_CAN1_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    USB_LP_CAN1_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    WWDG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xe.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    Error_Handler (Thumb, 8 bytes, Stack size 0 bytes, main.o(.text)) -

    [Stack]

    • Max Depth = 24 + In Cycle -
    • Call Chain = Error_Handler ⇒ Error_Handler (Cycle) -
    -
    [Calls]
    • >>   Error_Handler -
    • >>   __2printf -
    -
    [Called By]
    • >>   MX_USART1_UART_Init -
    • >>   MX_SPI1_Init -
    • >>   SystemClock_Config -
    • >>   Error_Handler -
    - -

    SystemClock_Config (Thumb, 88 bytes, Stack size 72 bytes, main.o(.text)) -

    [Stack]

    • Max Depth = 124
    • Call Chain = SystemClock_Config ⇒ HAL_RCC_ClockConfig ⇒ HAL_RCC_GetSysClockFreq -
    -
    [Calls]
    • >>   HAL_RCC_OscConfig -
    • >>   HAL_RCC_ClockConfig -
    • >>   Error_Handler -
    • >>   __aeabi_memclr4 -
    -
    [Called By]
    • >>   main -
    - -

    main (Thumb, 36 bytes, Stack size 0 bytes, main.o(.text)) -

    [Stack]

    • Max Depth = 760
    • Call Chain = main ⇒ EPD_2in36g_test ⇒ Paint_DrawNum ⇒ Paint_DrawString_EN ⇒ Paint_DrawChar ⇒ Paint_SetPixel ⇒ __2printf -
    -
    [Calls]
    • >>   MX_USART1_UART_Init -
    • >>   MX_SPI1_Init -
    • >>   MX_GPIO_Init -
    • >>   HAL_Init -
    • >>   HAL_Delay -
    • >>   EPD_2in36g_test -
    • >>   SystemClock_Config -
    -
    [Address Reference Count : 1]
    • entry9a.o(.ARM.Collect$$$$0000000B) -
    -

    MX_GPIO_Init (Thumb, 86 bytes, Stack size 32 bytes, gpio.o(.text)) -

    [Stack]

    • Max Depth = 72
    • Call Chain = MX_GPIO_Init ⇒ HAL_GPIO_Init -
    -
    [Calls]
    • >>   HAL_GPIO_WritePin -
    • >>   HAL_GPIO_Init -
    -
    [Called By]
    • >>   main -
    - -

    MX_SPI1_Init (Thumb, 62 bytes, Stack size 8 bytes, spi.o(.text)) -

    [Stack]

    • Max Depth = 88
    • Call Chain = MX_SPI1_Init ⇒ HAL_SPI_Init ⇒ HAL_SPI_MspInit ⇒ HAL_GPIO_Init -
    -
    [Calls]
    • >>   HAL_SPI_Init -
    • >>   Error_Handler -
    -
    [Called By]
    • >>   main -
    - -

    HAL_SPI_MspInit (Thumb, 80 bytes, Stack size 24 bytes, spi.o(.text)) -

    [Stack]

    • Max Depth = 64
    • Call Chain = HAL_SPI_MspInit ⇒ HAL_GPIO_Init -
    -
    [Calls]
    • >>   HAL_GPIO_Init -
    -
    [Called By]
    • >>   HAL_SPI_Init -
    - -

    HAL_SPI_MspDeInit (Thumb, 28 bytes, Stack size 0 bytes, spi.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_GPIO_DeInit -
    -
    [Called By]
    • >>   HAL_SPI_DeInit -
    - -

    MX_USART1_UART_Init (Thumb, 48 bytes, Stack size 8 bytes, usart.o(.text)) -

    [Stack]

    • Max Depth = 96
    • Call Chain = MX_USART1_UART_Init ⇒ HAL_UART_Init ⇒ HAL_UART_MspInit ⇒ HAL_GPIO_Init -
    -
    [Calls]
    • >>   HAL_UART_Init -
    • >>   Error_Handler -
    -
    [Called By]
    • >>   main -
    - -

    HAL_UART_MspInit (Thumb, 100 bytes, Stack size 32 bytes, usart.o(.text)) -

    [Stack]

    • Max Depth = 72
    • Call Chain = HAL_UART_MspInit ⇒ HAL_GPIO_Init -
    -
    [Calls]
    • >>   HAL_GPIO_Init -
    -
    [Called By]
    • >>   HAL_UART_Init -
    • >>   HAL_MultiProcessor_Init -
    • >>   HAL_LIN_Init -
    • >>   HAL_HalfDuplex_Init -
    - -

    HAL_UART_MspDeInit (Thumb, 30 bytes, Stack size 0 bytes, usart.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_GPIO_DeInit -
    -
    [Called By]
    • >>   HAL_UART_DeInit -
    - -

    fputc (Thumb, 20 bytes, Stack size 16 bytes, usart.o(.text)) -

    [Stack]

    • Max Depth = 72
    • Call Chain = fputc ⇒ HAL_UART_Transmit ⇒ UART_WaitOnFlagUntilTimeout -
    -
    [Calls]
    • >>   HAL_UART_Transmit -
    -
    [Address Reference Count : 1]
    • printf3.o(i.__0printf$3) -
    -

    NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f1xx_it.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    HardFault_Handler (Thumb, 8 bytes, Stack size 0 bytes, stm32f1xx_it.o(.text)) -

    [Stack]

    • Max Depth = 24
    • Call Chain = HardFault_Handler ⇒ __2printf -
    -
    [Calls]
    • >>   __2printf -
    -
    [Address Reference Count : 1]
    • startup_stm32f103xe.o(RESET) -
    -

    MemManage_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f1xx_it.o(.text)) -

    [Calls]

    • >>   MemManage_Handler -
    -
    [Called By]
    • >>   MemManage_Handler -
    -
    [Address Reference Count : 1]
    • startup_stm32f103xe.o(RESET) -
    -

    BusFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f1xx_it.o(.text)) -

    [Calls]

    • >>   BusFault_Handler -
    -
    [Called By]
    • >>   BusFault_Handler -
    -
    [Address Reference Count : 1]
    • startup_stm32f103xe.o(RESET) -
    -

    UsageFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f1xx_it.o(.text)) -

    [Calls]

    • >>   UsageFault_Handler -
    -
    [Called By]
    • >>   UsageFault_Handler -
    -
    [Address Reference Count : 1]
    • startup_stm32f103xe.o(RESET) -
    -

    SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f1xx_it.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    DebugMon_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f1xx_it.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    PendSV_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f1xx_it.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(RESET) -
    -

    SysTick_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f1xx_it.o(.text)) -

    [Calls]

    • >>   HAL_IncTick -
    -
    [Address Reference Count : 1]
    • startup_stm32f103xe.o(RESET) -
    -

    HAL_MspInit (Thumb, 52 bytes, Stack size 8 bytes, stm32f1xx_hal_msp.o(.text)) -

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_MspInit -
    -
    [Called By]
    • >>   HAL_Init -
    - -

    EPD_2in36g_test (Thumb, 966 bytes, Stack size 56 bytes, epd_2in36g_test.o(.text)) -

    [Stack]

    • Max Depth = 760
    • Call Chain = EPD_2in36g_test ⇒ Paint_DrawNum ⇒ Paint_DrawString_EN ⇒ Paint_DrawChar ⇒ Paint_SetPixel ⇒ __2printf -
    -
    [Calls]
    • >>   Paint_SetScale -
    • >>   Paint_DrawBitMap -
    • >>   Paint_SelectImage -
    • >>   Paint_NewImage -
    • >>   Paint_DrawString_EN -
    • >>   Paint_DrawString_CN -
    • >>   Paint_DrawRectangle -
    • >>   Paint_DrawPoint -
    • >>   Paint_DrawNum -
    • >>   Paint_DrawLine -
    • >>   Paint_DrawCircle -
    • >>   Paint_Clear -
    • >>   DEV_Module_Init -
    • >>   DEV_Module_Exit -
    • >>   HAL_Delay -
    • >>   EPD_2IN36G_Sleep -
    • >>   EPD_2IN36G_Init -
    • >>   EPD_2IN36G_Display -
    • >>   EPD_2IN36G_Clear -
    • >>   malloc -
    • >>   free -
    • >>   __2printf -
    -
    [Called By]
    • >>   main -
    - -

    EPD_2IN36G_Init (Thumb, 284 bytes, Stack size 8 bytes, epd_2in36g.o(.text)) -

    [Stack]

    • Max Depth = 120
    • Call Chain = EPD_2IN36G_Init ⇒ EPD_2IN36G_SendData ⇒ DEV_SPI_WriteByte ⇒ HAL_SPI_Transmit ⇒ SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout -
    -
    [Calls]
    • >>   HAL_GPIO_WritePin -
    • >>   HAL_Delay -
    • >>   EPD_2IN36G_SendData -
    • >>   EPD_2IN36G_SendCommand -
    -
    [Called By]
    • >>   EPD_2in36g_test -
    - -

    EPD_2IN36G_Clear (Thumb, 98 bytes, Stack size 24 bytes, epd_2in36g.o(.text)) -

    [Stack]

    • Max Depth = 144
    • Call Chain = EPD_2IN36G_Clear ⇒ EPD_2IN36G_TurnOnDisplay ⇒ EPD_2IN36G_SendData ⇒ DEV_SPI_WriteByte ⇒ HAL_SPI_Transmit ⇒ SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout -
    -
    [Calls]
    • >>   EPD_2IN36G_TurnOnDisplay -
    • >>   EPD_2IN36G_SendData -
    • >>   EPD_2IN36G_SendCommand -
    • >>   EPD_2IN36G_ReadBusyH -
    -
    [Called By]
    • >>   EPD_2in36g_test -
    - -

    EPD_2IN36G_Display (Thumb, 84 bytes, Stack size 32 bytes, epd_2in36g.o(.text)) -

    [Stack]

    • Max Depth = 152
    • Call Chain = EPD_2IN36G_Display ⇒ EPD_2IN36G_TurnOnDisplay ⇒ EPD_2IN36G_SendData ⇒ DEV_SPI_WriteByte ⇒ HAL_SPI_Transmit ⇒ SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout -
    -
    [Calls]
    • >>   EPD_2IN36G_TurnOnDisplay -
    • >>   EPD_2IN36G_SendData -
    • >>   EPD_2IN36G_SendCommand -
    • >>   EPD_2IN36G_ReadBusyH -
    -
    [Called By]
    • >>   EPD_2in36g_test -
    - -

    EPD_2IN36G_Sleep (Thumb, 30 bytes, Stack size 8 bytes, epd_2in36g.o(.text)) -

    [Stack]

    • Max Depth = 120
    • Call Chain = EPD_2IN36G_Sleep ⇒ EPD_2IN36G_SendData ⇒ DEV_SPI_WriteByte ⇒ HAL_SPI_Transmit ⇒ SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout -
    -
    [Calls]
    • >>   EPD_2IN36G_SendData -
    • >>   EPD_2IN36G_SendCommand -
    -
    [Called By]
    • >>   EPD_2in36g_test -
    - -

    DEV_SPI_WriteByte (Thumb, 18 bytes, Stack size 8 bytes, dev_config.o(.text)) -

    [Stack]

    • Max Depth = 96
    • Call Chain = DEV_SPI_WriteByte ⇒ HAL_SPI_Transmit ⇒ SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout -
    -
    [Calls]
    • >>   HAL_SPI_Transmit -
    -
    [Called By]
    • >>   EPD_2IN36G_SendData -
    • >>   EPD_2IN36G_SendCommand -
    - -

    DEV_Module_Init (Thumb, 38 bytes, Stack size 8 bytes, dev_config.o(.text)) -

    [Stack]

    • Max Depth = 8
    • Call Chain = DEV_Module_Init -
    -
    [Calls]
    • >>   HAL_GPIO_WritePin -
    -
    [Called By]
    • >>   EPD_2in36g_test -
    - -

    DEV_Module_Exit (Thumb, 38 bytes, Stack size 8 bytes, dev_config.o(.text)) -

    [Stack]

    • Max Depth = 8
    • Call Chain = DEV_Module_Exit -
    -
    [Calls]
    • >>   HAL_GPIO_WritePin -
    -
    [Called By]
    • >>   EPD_2in36g_test -
    - -

    Paint_NewImage (Thumb, 56 bytes, Stack size 16 bytes, gui_paint.o(.text)) -

    [Stack]

    • Max Depth = 16
    • Call Chain = Paint_NewImage -
    -
    [Called By]
    • >>   EPD_2in36g_test -
    - -

    Paint_SelectImage (Thumb, 6 bytes, Stack size 0 bytes, gui_paint.o(.text)) -

    [Called By]

    • >>   EPD_2in36g_test -
    - -

    Paint_SetRotate (Thumb, 44 bytes, Stack size 8 bytes, gui_paint.o(.text), UNUSED) -

    [Calls]

    • >>   __2printf -
    - -

    Paint_SetScale (Thumb, 80 bytes, Stack size 8 bytes, gui_paint.o(.text)) -

    [Stack]

    • Max Depth = 32
    • Call Chain = Paint_SetScale ⇒ __2printf -
    -
    [Calls]
    • >>   __2printf -
    -
    [Called By]
    • >>   EPD_2in36g_test -
    - -

    Paint_SetMirroring (Thumb, 62 bytes, Stack size 8 bytes, gui_paint.o(.text), UNUSED) -

    [Calls]

    • >>   __2printf -
    - -

    Paint_SetPixel (Thumb, 238 bytes, Stack size 16 bytes, gui_paint.o(.text)) -

    [Stack]

    • Max Depth = 40
    • Call Chain = Paint_SetPixel ⇒ __2printf -
    -
    [Calls]
    • >>   __2printf -
    -
    [Called By]
    • >>   Paint_DrawString_CN -
    • >>   Paint_DrawPoint -
    • >>   Paint_ClearWindows -
    • >>   Paint_DrawBitMap_Paste -
    • >>   Paint_DrawChar -
    - -

    Paint_Clear (Thumb, 156 bytes, Stack size 12 bytes, gui_paint.o(.text)) -

    [Stack]

    • Max Depth = 12
    • Call Chain = Paint_Clear -
    -
    [Called By]
    • >>   EPD_2in36g_test -
    - -

    Paint_ClearWindows (Thumb, 52 bytes, Stack size 32 bytes, gui_paint.o(.text), UNUSED) -

    [Calls]

    • >>   Paint_SetPixel -
    - -

    Paint_DrawPoint (Thumb, 180 bytes, Stack size 40 bytes, gui_paint.o(.text)) -

    [Stack]

    • Max Depth = 80
    • Call Chain = Paint_DrawPoint ⇒ Paint_SetPixel ⇒ __2printf -
    -
    [Calls]
    • >>   Paint_SetPixel -
    • >>   __2printf -
    -
    [Called By]
    • >>   Paint_DrawLine -
    • >>   Paint_DrawCircle -
    • >>   EPD_2in36g_test -
    - -

    Paint_DrawLine (Thumb, 662 bytes, Stack size 48 bytes, gui_paint.o(.text)) -

    [Stack]

    • Max Depth = 128
    • Call Chain = Paint_DrawLine ⇒ Paint_DrawPoint ⇒ Paint_SetPixel ⇒ __2printf -
    -
    [Calls]
    • >>   Paint_DrawPoint -
    • >>   __2printf -
    -
    [Called By]
    • >>   Paint_DrawRectangle -
    • >>   EPD_2in36g_test -
    - -

    Paint_DrawRectangle (Thumb, 170 bytes, Stack size 48 bytes, gui_paint.o(.text)) -

    [Stack]

    • Max Depth = 176
    • Call Chain = Paint_DrawRectangle ⇒ Paint_DrawLine ⇒ Paint_DrawPoint ⇒ Paint_SetPixel ⇒ __2printf -
    -
    [Calls]
    • >>   Paint_DrawLine -
    • >>   __2printf -
    -
    [Called By]
    • >>   EPD_2in36g_test -
    - -

    Paint_DrawCircle (Thumb, 528 bytes, Stack size 72 bytes, gui_paint.o(.text)) -

    [Stack]

    • Max Depth = 152
    • Call Chain = Paint_DrawCircle ⇒ Paint_DrawPoint ⇒ Paint_SetPixel ⇒ __2printf -
    -
    [Calls]
    • >>   Paint_DrawPoint -
    • >>   __2printf -
    -
    [Called By]
    • >>   EPD_2in36g_test -
    - -

    Paint_DrawChar (Thumb, 172 bytes, Stack size 40 bytes, gui_paint.o(.text)) -

    [Stack]

    • Max Depth = 80
    • Call Chain = Paint_DrawChar ⇒ Paint_SetPixel ⇒ __2printf -
    -
    [Calls]
    • >>   Paint_SetPixel -
    • >>   __2printf -
    -
    [Called By]
    • >>   Paint_DrawTime -
    • >>   Paint_DrawString_EN -
    - -

    Paint_DrawString_EN (Thumb, 116 bytes, Stack size 48 bytes, gui_paint.o(.text)) -

    [Stack]

    • Max Depth = 128
    • Call Chain = Paint_DrawString_EN ⇒ Paint_DrawChar ⇒ Paint_SetPixel ⇒ __2printf -
    -
    [Calls]
    • >>   Paint_DrawChar -
    • >>   __2printf -
    -
    [Called By]
    • >>   Paint_DrawNum -
    • >>   EPD_2in36g_test -
    - -

    Paint_DrawString_CN (Thumb, 518 bytes, Stack size 40 bytes, gui_paint.o(.text)) -

    [Stack]

    • Max Depth = 80
    • Call Chain = Paint_DrawString_CN ⇒ Paint_SetPixel ⇒ __2printf -
    -
    [Calls]
    • >>   Paint_SetPixel -
    -
    [Called By]
    • >>   EPD_2in36g_test -
    - -

    Paint_DrawNum (Thumb, 140 bytes, Stack size 576 bytes, gui_paint.o(.text)) -

    [Stack]

    • Max Depth = 704
    • Call Chain = Paint_DrawNum ⇒ Paint_DrawString_EN ⇒ Paint_DrawChar ⇒ Paint_SetPixel ⇒ __2printf -
    -
    [Calls]
    • >>   Paint_DrawString_EN -
    • >>   __2printf -
    • >>   __aeabi_memclr4 -
    -
    [Called By]
    • >>   EPD_2in36g_test -
    - -

    Paint_DrawTime (Thumb, 282 bytes, Stack size 72 bytes, gui_paint.o(.text), UNUSED) -

    [Calls]

    • >>   Paint_DrawChar -
    - -

    Paint_DrawBitMap (Thumb, 46 bytes, Stack size 16 bytes, gui_paint.o(.text)) -

    [Stack]

    • Max Depth = 16
    • Call Chain = Paint_DrawBitMap -
    -
    [Called By]
    • >>   EPD_2in36g_test -
    - -

    Paint_DrawBitMap_Paste (Thumb, 110 bytes, Stack size 56 bytes, gui_paint.o(.text), UNUSED) -

    [Calls]

    • >>   Paint_SetPixel -
    - -

    Paint_DrawBitMap_Block (Thumb, 54 bytes, Stack size 20 bytes, gui_paint.o(.text), UNUSED) - -

    SystemInit (Thumb, 60 bytes, Stack size 0 bytes, system_stm32f1xx.o(.text)) -
    [Address Reference Count : 1]

    • startup_stm32f103xe.o(.text) -
    -

    SystemCoreClockUpdate (Thumb, 108 bytes, Stack size 0 bytes, system_stm32f1xx.o(.text), UNUSED) - -

    HAL_SPI_Init (Thumb, 180 bytes, Stack size 16 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Stack]

    • Max Depth = 80
    • Call Chain = HAL_SPI_Init ⇒ HAL_SPI_MspInit ⇒ HAL_GPIO_Init -
    -
    [Calls]
    • >>   HAL_SPI_MspInit -
    -
    [Called By]
    • >>   MX_SPI1_Init -
    - -

    HAL_SPI_DeInit (Thumb, 48 bytes, Stack size 8 bytes, stm32f1xx_hal_spi.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_SPI_MspDeInit -
    - -

    HAL_SPI_Transmit (Thumb, 412 bytes, Stack size 40 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Stack]

    • Max Depth = 88
    • Call Chain = HAL_SPI_Transmit ⇒ SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout -
    -
    [Calls]
    • >>   HAL_GetTick -
    • >>   SPI_EndRxTxTransaction -
    -
    [Called By]
    • >>   DEV_SPI_WriteByte -
    - -

    HAL_SPI_TransmitReceive (Thumb, 510 bytes, Stack size 40 bytes, stm32f1xx_hal_spi.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_GetTick -
    • >>   SPI_EndRxTxTransaction -
    -
    [Called By]
    • >>   HAL_SPI_Receive -
    - -

    HAL_SPI_Receive (Thumb, 366 bytes, Stack size 40 bytes, stm32f1xx_hal_spi.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_GetTick -
    • >>   HAL_SPI_TransmitReceive -
    • >>   SPI_EndRxTransaction -
    - -

    HAL_SPI_TxCpltCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Called By]

    • >>   SPI_DMATransmitCplt -
    • >>   SPI_CloseTx_ISR -
    - -

    HAL_SPI_ErrorCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Called By]

    • >>   HAL_SPI_IRQHandler -
    • >>   SPI_DMAAbortOnError -
    • >>   SPI_DMATransmitReceiveCplt -
    • >>   SPI_DMAReceiveCplt -
    • >>   SPI_DMATransmitCplt -
    • >>   SPI_DMAError -
    • >>   SPI_CloseRxTx_ISR -
    • >>   SPI_CloseRx_ISR -
    • >>   SPI_CloseTx_ISR -
    - -

    HAL_SPI_Transmit_IT (Thumb, 162 bytes, Stack size 4 bytes, stm32f1xx_hal_spi.o(.text), UNUSED) - -

    HAL_SPI_RxCpltCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Called By]

    • >>   SPI_DMAReceiveCplt -
    • >>   SPI_CloseRxTx_ISR -
    • >>   SPI_CloseRx_ISR -
    - -

    HAL_SPI_TxRxCpltCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Called By]

    • >>   SPI_DMATransmitReceiveCplt -
    • >>   SPI_CloseRxTx_ISR -
    - -

    HAL_SPI_TransmitReceive_IT (Thumb, 188 bytes, Stack size 12 bytes, stm32f1xx_hal_spi.o(.text), UNUSED) -

    [Called By]

    • >>   HAL_SPI_Receive_IT -
    - -

    HAL_SPI_Receive_IT (Thumb, 176 bytes, Stack size 12 bytes, stm32f1xx_hal_spi.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_SPI_TransmitReceive_IT -
    - -

    HAL_SPI_TxHalfCpltCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Called By]

    • >>   SPI_DMAHalfTransmitCplt -
    - -

    HAL_SPI_Transmit_DMA (Thumb, 208 bytes, Stack size 24 bytes, stm32f1xx_hal_spi.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_DMA_Start_IT -
    - -

    HAL_SPI_RxHalfCpltCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Called By]

    • >>   SPI_DMAHalfReceiveCplt -
    - -

    HAL_SPI_TxRxHalfCpltCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Called By]

    • >>   SPI_DMAHalfTransmitReceiveCplt -
    - -

    HAL_SPI_TransmitReceive_DMA (Thumb, 302 bytes, Stack size 24 bytes, stm32f1xx_hal_spi.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_DMA_Start_IT -
    -
    [Called By]
    • >>   HAL_SPI_Receive_DMA -
    - -

    HAL_SPI_Receive_DMA (Thumb, 278 bytes, Stack size 24 bytes, stm32f1xx_hal_spi.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_DMA_Start_IT -
    • >>   HAL_SPI_TransmitReceive_DMA -
    - -

    HAL_SPI_Abort (Thumb, 290 bytes, Stack size 32 bytes, stm32f1xx_hal_spi.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_DMA_Abort -
    - -

    HAL_SPI_AbortCpltCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Called By]

    • >>   HAL_SPI_Abort_IT -
    • >>   SPI_DMATxAbortCallback -
    • >>   SPI_DMARxAbortCallback -
    - -

    HAL_SPI_Abort_IT (Thumb, 328 bytes, Stack size 40 bytes, stm32f1xx_hal_spi.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_SPI_AbortCpltCallback -
    • >>   HAL_DMA_Abort_IT -
    - -

    HAL_SPI_DMAPause (Thumb, 38 bytes, Stack size 0 bytes, stm32f1xx_hal_spi.o(.text), UNUSED) - -

    HAL_SPI_DMAResume (Thumb, 38 bytes, Stack size 0 bytes, stm32f1xx_hal_spi.o(.text), UNUSED) - -

    HAL_SPI_DMAStop (Thumb, 68 bytes, Stack size 16 bytes, stm32f1xx_hal_spi.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_DMA_Abort -
    - -

    HAL_SPI_IRQHandler (Thumb, 250 bytes, Stack size 16 bytes, stm32f1xx_hal_spi.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_SPI_ErrorCallback -
    • >>   HAL_DMA_Abort_IT -
    - -

    HAL_SPI_GetState (Thumb, 6 bytes, Stack size 0 bytes, stm32f1xx_hal_spi.o(.text), UNUSED) - -

    HAL_SPI_GetError (Thumb, 4 bytes, Stack size 0 bytes, stm32f1xx_hal_spi.o(.text), UNUSED) - -

    HAL_InitTick (Thumb, 58 bytes, Stack size 16 bytes, stm32f1xx_hal.o(.text)) -

    [Stack]

    • Max Depth = 20
    • Call Chain = HAL_InitTick ⇒ HAL_NVIC_SetPriority -
    -
    [Calls]
    • >>   HAL_SYSTICK_Config -
    • >>   HAL_NVIC_SetPriority -
    -
    [Called By]
    • >>   HAL_RCC_ClockConfig -
    • >>   HAL_Init -
    • >>   HAL_RCC_DeInit -
    • >>   HAL_SetTickFreq -
    - -

    HAL_Init (Thumb, 32 bytes, Stack size 8 bytes, stm32f1xx_hal.o(.text)) -

    [Stack]

    • Max Depth = 28
    • Call Chain = HAL_Init ⇒ HAL_InitTick ⇒ HAL_NVIC_SetPriority -
    -
    [Calls]
    • >>   HAL_MspInit -
    • >>   HAL_InitTick -
    • >>   HAL_NVIC_SetPriorityGrouping -
    -
    [Called By]
    • >>   main -
    - -

    HAL_MspDeInit (Thumb, 2 bytes, Stack size 0 bytes, stm32f1xx_hal.o(.text), UNUSED) -

    [Called By]

    • >>   HAL_DeInit -
    - -

    HAL_DeInit (Thumb, 26 bytes, Stack size 8 bytes, stm32f1xx_hal.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_MspDeInit -
    - -

    HAL_IncTick (Thumb, 12 bytes, Stack size 0 bytes, stm32f1xx_hal.o(.text)) -

    [Called By]

    • >>   SysTick_Handler -
    - -

    HAL_GetTick (Thumb, 6 bytes, Stack size 0 bytes, stm32f1xx_hal.o(.text)) -

    [Called By]

    • >>   HAL_UART_Transmit -
    • >>   HAL_RCC_OscConfig -
    • >>   HAL_RCC_ClockConfig -
    • >>   HAL_Delay -
    • >>   HAL_DMA_PollForTransfer -
    • >>   HAL_RCC_DeInit -
    • >>   HAL_SPI_Receive -
    • >>   HAL_SPI_TransmitReceive -
    • >>   SPI_DMARxAbortCallback -
    • >>   SPI_DMATransmitReceiveCplt -
    • >>   SPI_DMAReceiveCplt -
    • >>   SPI_DMATransmitCplt -
    • >>   SPI_CloseRxTx_ISR -
    • >>   SPI_CloseRx_ISR -
    • >>   SPI_CloseTx_ISR -
    • >>   SPI_WaitFlagStateUntilTimeout -
    • >>   HAL_SPI_Transmit -
    • >>   HAL_UART_Receive -
    • >>   UART_WaitOnFlagUntilTimeout -
    - -

    HAL_GetTickPrio (Thumb, 6 bytes, Stack size 0 bytes, stm32f1xx_hal.o(.text), UNUSED) - -

    HAL_SetTickFreq (Thumb, 30 bytes, Stack size 16 bytes, stm32f1xx_hal.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_InitTick -
    - -

    HAL_GetTickFreq (Thumb, 6 bytes, Stack size 0 bytes, stm32f1xx_hal.o(.text), UNUSED) - -

    HAL_Delay (Thumb, 34 bytes, Stack size 16 bytes, stm32f1xx_hal.o(.text)) -

    [Stack]

    • Max Depth = 16
    • Call Chain = HAL_Delay -
    -
    [Calls]
    • >>   HAL_GetTick -
    -
    [Called By]
    • >>   EPD_2in36g_test -
    • >>   main -
    • >>   EPD_2IN36G_Init -
    • >>   EPD_2IN36G_ReadBusyH -
    - -

    HAL_SuspendTick (Thumb, 14 bytes, Stack size 0 bytes, stm32f1xx_hal.o(.text), UNUSED) - -

    HAL_ResumeTick (Thumb, 14 bytes, Stack size 0 bytes, stm32f1xx_hal.o(.text), UNUSED) - -

    HAL_GetHalVersion (Thumb, 4 bytes, Stack size 0 bytes, stm32f1xx_hal.o(.text), UNUSED) - -

    HAL_GetREVID (Thumb, 8 bytes, Stack size 0 bytes, stm32f1xx_hal.o(.text), UNUSED) - -

    HAL_GetDEVID (Thumb, 10 bytes, Stack size 0 bytes, stm32f1xx_hal.o(.text), UNUSED) - -

    HAL_GetUIDw0 (Thumb, 6 bytes, Stack size 0 bytes, stm32f1xx_hal.o(.text), UNUSED) - -

    HAL_GetUIDw1 (Thumb, 6 bytes, Stack size 0 bytes, stm32f1xx_hal.o(.text), UNUSED) - -

    HAL_GetUIDw2 (Thumb, 6 bytes, Stack size 0 bytes, stm32f1xx_hal.o(.text), UNUSED) - -

    HAL_DBGMCU_EnableDBGSleepMode (Thumb, 12 bytes, Stack size 0 bytes, stm32f1xx_hal.o(.text), UNUSED) - -

    HAL_DBGMCU_DisableDBGSleepMode (Thumb, 12 bytes, Stack size 0 bytes, stm32f1xx_hal.o(.text), UNUSED) - -

    HAL_DBGMCU_EnableDBGStopMode (Thumb, 12 bytes, Stack size 0 bytes, stm32f1xx_hal.o(.text), UNUSED) - -

    HAL_DBGMCU_DisableDBGStopMode (Thumb, 12 bytes, Stack size 0 bytes, stm32f1xx_hal.o(.text), UNUSED) - -

    HAL_DBGMCU_EnableDBGStandbyMode (Thumb, 12 bytes, Stack size 0 bytes, stm32f1xx_hal.o(.text), UNUSED) - -

    HAL_DBGMCU_DisableDBGStandbyMode (Thumb, 12 bytes, Stack size 0 bytes, stm32f1xx_hal.o(.text), UNUSED) - -

    HAL_RCC_DeInit (Thumb, 250 bytes, Stack size 24 bytes, stm32f1xx_hal_rcc.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_InitTick -
    • >>   HAL_GetTick -
    - -

    HAL_RCC_OscConfig (Thumb, 1080 bytes, Stack size 40 bytes, stm32f1xx_hal_rcc.o(.text)) -

    [Stack]

    • Max Depth = 44
    • Call Chain = HAL_RCC_OscConfig ⇒ RCC_Delay -
    -
    [Calls]
    • >>   RCC_Delay -
    • >>   HAL_GetTick -
    -
    [Called By]
    • >>   SystemClock_Config -
    - -

    HAL_RCC_GetSysClockFreq (Thumb, 88 bytes, Stack size 20 bytes, stm32f1xx_hal_rcc.o(.text)) -

    [Stack]

    • Max Depth = 20
    • Call Chain = HAL_RCC_GetSysClockFreq -
    -
    [Called By]
    • >>   HAL_RCC_ClockConfig -
    - -

    HAL_RCC_ClockConfig (Thumb, 364 bytes, Stack size 32 bytes, stm32f1xx_hal_rcc.o(.text)) -

    [Stack]

    • Max Depth = 52
    • Call Chain = HAL_RCC_ClockConfig ⇒ HAL_RCC_GetSysClockFreq -
    -
    [Calls]
    • >>   HAL_RCC_GetSysClockFreq -
    • >>   HAL_InitTick -
    • >>   HAL_GetTick -
    -
    [Called By]
    • >>   SystemClock_Config -
    - -

    HAL_RCC_MCOConfig (Thumb, 64 bytes, Stack size 40 bytes, stm32f1xx_hal_rcc.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_GPIO_Init -
    - -

    HAL_RCC_EnableCSS (Thumb, 8 bytes, Stack size 0 bytes, stm32f1xx_hal_rcc.o(.text), UNUSED) - -

    HAL_RCC_DisableCSS (Thumb, 8 bytes, Stack size 0 bytes, stm32f1xx_hal_rcc.o(.text), UNUSED) - -

    HAL_RCC_GetHCLKFreq (Thumb, 6 bytes, Stack size 0 bytes, stm32f1xx_hal_rcc.o(.text)) -

    [Called By]

    • >>   HAL_RCC_GetPCLK2Freq -
    • >>   HAL_RCC_GetPCLK1Freq -
    - -

    HAL_RCC_GetPCLK1Freq (Thumb, 22 bytes, Stack size 4 bytes, stm32f1xx_hal_rcc.o(.text)) -

    [Stack]

    • Max Depth = 4
    • Call Chain = HAL_RCC_GetPCLK1Freq -
    -
    [Calls]
    • >>   HAL_RCC_GetHCLKFreq -
    -
    [Called By]
    • >>   UART_SetConfig -
    - -

    HAL_RCC_GetPCLK2Freq (Thumb, 22 bytes, Stack size 4 bytes, stm32f1xx_hal_rcc.o(.text)) -

    [Stack]

    • Max Depth = 4
    • Call Chain = HAL_RCC_GetPCLK2Freq -
    -
    [Calls]
    • >>   HAL_RCC_GetHCLKFreq -
    -
    [Called By]
    • >>   UART_SetConfig -
    - -

    HAL_RCC_GetOscConfig (Thumb, 168 bytes, Stack size 0 bytes, stm32f1xx_hal_rcc.o(.text), UNUSED) - -

    HAL_RCC_GetClockConfig (Thumb, 52 bytes, Stack size 0 bytes, stm32f1xx_hal_rcc.o(.text), UNUSED) - -

    HAL_RCC_CSSCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32f1xx_hal_rcc.o(.text), UNUSED) -

    [Called By]

    • >>   HAL_RCC_NMI_IRQHandler -
    - -

    HAL_RCC_NMI_IRQHandler (Thumb, 22 bytes, Stack size 8 bytes, stm32f1xx_hal_rcc.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_RCC_CSSCallback -
    - -

    HAL_GPIO_Init (Thumb, 524 bytes, Stack size 40 bytes, stm32f1xx_hal_gpio.o(.text)) -

    [Stack]

    • Max Depth = 40
    • Call Chain = HAL_GPIO_Init -
    -
    [Called By]
    • >>   HAL_UART_MspInit -
    • >>   HAL_SPI_MspInit -
    • >>   MX_GPIO_Init -
    • >>   HAL_RCC_MCOConfig -
    - -

    HAL_GPIO_DeInit (Thumb, 320 bytes, Stack size 36 bytes, stm32f1xx_hal_gpio.o(.text), UNUSED) -

    [Called By]

    • >>   HAL_UART_MspDeInit -
    • >>   HAL_SPI_MspDeInit -
    - -

    HAL_GPIO_ReadPin (Thumb, 14 bytes, Stack size 0 bytes, stm32f1xx_hal_gpio.o(.text)) -

    [Called By]

    • >>   EPD_2IN36G_ReadBusyH -
    - -

    HAL_GPIO_WritePin (Thumb, 14 bytes, Stack size 0 bytes, stm32f1xx_hal_gpio.o(.text)) -

    [Called By]

    • >>   DEV_Module_Init -
    • >>   DEV_Module_Exit -
    • >>   MX_GPIO_Init -
    • >>   EPD_2IN36G_Init -
    • >>   EPD_2IN36G_SendData -
    • >>   EPD_2IN36G_SendCommand -
    - -

    HAL_GPIO_TogglePin (Thumb, 16 bytes, Stack size 0 bytes, stm32f1xx_hal_gpio.o(.text), UNUSED) - -

    HAL_GPIO_LockPin (Thumb, 42 bytes, Stack size 4 bytes, stm32f1xx_hal_gpio.o(.text), UNUSED) - -

    HAL_GPIO_EXTI_Callback (Thumb, 2 bytes, Stack size 0 bytes, stm32f1xx_hal_gpio.o(.text), UNUSED) -

    [Called By]

    • >>   HAL_GPIO_EXTI_IRQHandler -
    - -

    HAL_GPIO_EXTI_IRQHandler (Thumb, 18 bytes, Stack size 8 bytes, stm32f1xx_hal_gpio.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_GPIO_EXTI_Callback -
    - -

    HAL_DMA_Init (Thumb, 144 bytes, Stack size 4 bytes, stm32f1xx_hal_dma.o(.text), UNUSED) - -

    HAL_DMA_DeInit (Thumb, 126 bytes, Stack size 0 bytes, stm32f1xx_hal_dma.o(.text), UNUSED) - -

    HAL_DMA_Start (Thumb, 88 bytes, Stack size 16 bytes, stm32f1xx_hal_dma.o(.text), UNUSED) -

    [Calls]

    • >>   DMA_SetConfig -
    - -

    HAL_DMA_Start_IT (Thumb, 124 bytes, Stack size 16 bytes, stm32f1xx_hal_dma.o(.text), UNUSED) -

    [Calls]

    • >>   DMA_SetConfig -
    -
    [Called By]
    • >>   HAL_SPI_Receive_DMA -
    • >>   HAL_SPI_TransmitReceive_DMA -
    • >>   HAL_SPI_Transmit_DMA -
    • >>   HAL_UART_Receive_DMA -
    • >>   HAL_UART_Transmit_DMA -
    - -

    HAL_DMA_Abort (Thumb, 72 bytes, Stack size 0 bytes, stm32f1xx_hal_dma.o(.text), UNUSED) -

    [Called By]

    • >>   HAL_SPI_DMAStop -
    • >>   HAL_SPI_Abort -
    • >>   HAL_UART_AbortReceive -
    • >>   HAL_UART_AbortTransmit -
    • >>   HAL_UART_Abort -
    • >>   HAL_UART_DMAStop -
    - -

    HAL_DMA_Abort_IT (Thumb, 318 bytes, Stack size 40 bytes, stm32f1xx_hal_dma.o(.text), UNUSED) -

    [Called By]

    • >>   HAL_SPI_IRQHandler -
    • >>   HAL_SPI_Abort_IT -
    • >>   HAL_UART_IRQHandler -
    • >>   HAL_UART_AbortReceive_IT -
    • >>   HAL_UART_AbortTransmit_IT -
    • >>   HAL_UART_Abort_IT -
    - -

    HAL_DMA_PollForTransfer (Thumb, 1316 bytes, Stack size 56 bytes, stm32f1xx_hal_dma.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_GetTick -
    - -

    HAL_DMA_IRQHandler (Thumb, 672 bytes, Stack size 40 bytes, stm32f1xx_hal_dma.o(.text), UNUSED) - -

    HAL_DMA_RegisterCallback (Thumb, 80 bytes, Stack size 0 bytes, stm32f1xx_hal_dma.o(.text), UNUSED) - -

    HAL_DMA_UnRegisterCallback (Thumb, 86 bytes, Stack size 0 bytes, stm32f1xx_hal_dma.o(.text), UNUSED) - -

    HAL_DMA_GetState (Thumb, 6 bytes, Stack size 0 bytes, stm32f1xx_hal_dma.o(.text), UNUSED) - -

    HAL_DMA_GetError (Thumb, 4 bytes, Stack size 0 bytes, stm32f1xx_hal_dma.o(.text), UNUSED) -

    [Called By]

    • >>   HAL_UART_AbortReceive -
    • >>   HAL_UART_AbortTransmit -
    • >>   HAL_UART_Abort -
    - -

    HAL_NVIC_SetPriorityGrouping (Thumb, 30 bytes, Stack size 0 bytes, stm32f1xx_hal_cortex.o(.text)) -

    [Called By]

    • >>   HAL_Init -
    - -

    HAL_NVIC_SetPriority (Thumb, 98 bytes, Stack size 4 bytes, stm32f1xx_hal_cortex.o(.text)) -

    [Stack]

    • Max Depth = 4
    • Call Chain = HAL_NVIC_SetPriority -
    -
    [Called By]
    • >>   HAL_InitTick -
    - -

    HAL_NVIC_EnableIRQ (Thumb, 28 bytes, Stack size 0 bytes, stm32f1xx_hal_cortex.o(.text), UNUSED) - -

    HAL_NVIC_DisableIRQ (Thumb, 36 bytes, Stack size 0 bytes, stm32f1xx_hal_cortex.o(.text), UNUSED) - -

    HAL_NVIC_SystemReset (Thumb, 26 bytes, Stack size 0 bytes, stm32f1xx_hal_cortex.o(.text), UNUSED) - -

    HAL_SYSTICK_Config (Thumb, 36 bytes, Stack size 0 bytes, stm32f1xx_hal_cortex.o(.text)) -

    [Called By]

    • >>   HAL_InitTick -
    - -

    HAL_NVIC_GetPriorityGrouping (Thumb, 10 bytes, Stack size 0 bytes, stm32f1xx_hal_cortex.o(.text), UNUSED) - -

    HAL_NVIC_GetPriority (Thumb, 94 bytes, Stack size 8 bytes, stm32f1xx_hal_cortex.o(.text), UNUSED) - -

    HAL_NVIC_SetPendingIRQ (Thumb, 28 bytes, Stack size 0 bytes, stm32f1xx_hal_cortex.o(.text), UNUSED) - -

    HAL_NVIC_GetPendingIRQ (Thumb, 42 bytes, Stack size 0 bytes, stm32f1xx_hal_cortex.o(.text), UNUSED) - -

    HAL_NVIC_ClearPendingIRQ (Thumb, 28 bytes, Stack size 0 bytes, stm32f1xx_hal_cortex.o(.text), UNUSED) - -

    HAL_NVIC_GetActive (Thumb, 42 bytes, Stack size 0 bytes, stm32f1xx_hal_cortex.o(.text), UNUSED) - -

    HAL_SYSTICK_CLKSourceConfig (Thumb, 28 bytes, Stack size 0 bytes, stm32f1xx_hal_cortex.o(.text), UNUSED) - -

    HAL_SYSTICK_Callback (Thumb, 2 bytes, Stack size 0 bytes, stm32f1xx_hal_cortex.o(.text), UNUSED) -

    [Called By]

    • >>   HAL_SYSTICK_IRQHandler -
    - -

    HAL_SYSTICK_IRQHandler (Thumb, 8 bytes, Stack size 8 bytes, stm32f1xx_hal_cortex.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_SYSTICK_Callback -
    - -

    HAL_UART_Init (Thumb, 100 bytes, Stack size 16 bytes, stm32f1xx_hal_uart.o(.text)) -

    [Stack]

    • Max Depth = 88
    • Call Chain = HAL_UART_Init ⇒ HAL_UART_MspInit ⇒ HAL_GPIO_Init -
    -
    [Calls]
    • >>   HAL_UART_MspInit -
    • >>   UART_SetConfig -
    -
    [Called By]
    • >>   MX_USART1_UART_Init -
    - -

    HAL_HalfDuplex_Init (Thumb, 110 bytes, Stack size 16 bytes, stm32f1xx_hal_uart.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_UART_MspInit -
    • >>   UART_SetConfig -
    - -

    HAL_LIN_Init (Thumb, 130 bytes, Stack size 16 bytes, stm32f1xx_hal_uart.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_UART_MspInit -
    • >>   UART_SetConfig -
    - -

    HAL_MultiProcessor_Init (Thumb, 146 bytes, Stack size 24 bytes, stm32f1xx_hal_uart.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_UART_MspInit -
    • >>   UART_SetConfig -
    - -

    HAL_UART_DeInit (Thumb, 52 bytes, Stack size 8 bytes, stm32f1xx_hal_uart.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_UART_MspDeInit -
    - -

    HAL_UART_Transmit (Thumb, 202 bytes, Stack size 32 bytes, stm32f1xx_hal_uart.o(.text)) -

    [Stack]

    • Max Depth = 56
    • Call Chain = HAL_UART_Transmit ⇒ UART_WaitOnFlagUntilTimeout -
    -
    [Calls]
    • >>   HAL_GetTick -
    • >>   UART_WaitOnFlagUntilTimeout -
    -
    [Called By]
    • >>   fputc -
    - -

    HAL_UART_Receive (Thumb, 212 bytes, Stack size 32 bytes, stm32f1xx_hal_uart.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_GetTick -
    • >>   UART_WaitOnFlagUntilTimeout -
    - -

    HAL_UART_Transmit_IT (Thumb, 66 bytes, Stack size 0 bytes, stm32f1xx_hal_uart.o(.text), UNUSED) - -

    HAL_UART_Receive_IT (Thumb, 86 bytes, Stack size 0 bytes, stm32f1xx_hal_uart.o(.text), UNUSED) - -

    HAL_UART_ErrorCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32f1xx_hal_uart.o(.text)) -

    [Called By]

    • >>   HAL_UART_IRQHandler -
    • >>   UART_DMAAbortOnError -
    • >>   UART_DMAError -
    - -

    HAL_UART_TxHalfCpltCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32f1xx_hal_uart.o(.text)) -

    [Called By]

    • >>   UART_DMATxHalfCplt -
    - -

    HAL_UART_TxCpltCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32f1xx_hal_uart.o(.text)) -

    [Called By]

    • >>   UART_EndTransmit_IT -
    • >>   UART_DMATransmitCplt -
    - -

    HAL_UART_Transmit_DMA (Thumb, 138 bytes, Stack size 24 bytes, stm32f1xx_hal_uart.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_DMA_Start_IT -
    - -

    HAL_UART_RxHalfCpltCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32f1xx_hal_uart.o(.text)) -

    [Called By]

    • >>   UART_DMARxHalfCplt -
    - -

    HAL_UART_RxCpltCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32f1xx_hal_uart.o(.text)) -

    [Called By]

    • >>   UART_Receive_IT -
    • >>   UART_DMAReceiveCplt -
    - -

    HAL_UART_Receive_DMA (Thumb, 150 bytes, Stack size 32 bytes, stm32f1xx_hal_uart.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_DMA_Start_IT -
    - -

    HAL_UART_DMAPause (Thumb, 102 bytes, Stack size 0 bytes, stm32f1xx_hal_uart.o(.text), UNUSED) - -

    HAL_UART_DMAResume (Thumb, 98 bytes, Stack size 4 bytes, stm32f1xx_hal_uart.o(.text), UNUSED) - -

    HAL_UART_DMAStop (Thumb, 88 bytes, Stack size 8 bytes, stm32f1xx_hal_uart.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_DMA_Abort -
    • >>   UART_EndTxTransfer -
    • >>   UART_EndRxTransfer -
    - -

    HAL_UART_Abort (Thumb, 148 bytes, Stack size 16 bytes, stm32f1xx_hal_uart.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_DMA_GetError -
    • >>   HAL_DMA_Abort -
    - -

    HAL_UART_AbortTransmit (Thumb, 80 bytes, Stack size 16 bytes, stm32f1xx_hal_uart.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_DMA_GetError -
    • >>   HAL_DMA_Abort -
    - -

    HAL_UART_AbortReceive (Thumb, 90 bytes, Stack size 16 bytes, stm32f1xx_hal_uart.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_DMA_GetError -
    • >>   HAL_DMA_Abort -
    - -

    HAL_UART_AbortCpltCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32f1xx_hal_uart.o(.text)) -

    [Called By]

    • >>   HAL_UART_Abort_IT -
    • >>   UART_DMATxAbortCallback -
    • >>   UART_DMARxAbortCallback -
    - -

    HAL_UART_Abort_IT (Thumb, 178 bytes, Stack size 16 bytes, stm32f1xx_hal_uart.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_DMA_Abort_IT -
    • >>   HAL_UART_AbortCpltCallback -
    - -

    HAL_UART_AbortTransmitCpltCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32f1xx_hal_uart.o(.text)) -

    [Called By]

    • >>   HAL_UART_AbortTransmit_IT -
    • >>   UART_DMATxOnlyAbortCallback -
    - -

    HAL_UART_AbortTransmit_IT (Thumb, 94 bytes, Stack size 8 bytes, stm32f1xx_hal_uart.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_DMA_Abort_IT -
    • >>   HAL_UART_AbortTransmitCpltCallback -
    - -

    HAL_UART_AbortReceiveCpltCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32f1xx_hal_uart.o(.text)) -

    [Called By]

    • >>   HAL_UART_AbortReceive_IT -
    • >>   UART_DMARxOnlyAbortCallback -
    - -

    HAL_UART_AbortReceive_IT (Thumb, 104 bytes, Stack size 8 bytes, stm32f1xx_hal_uart.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_DMA_Abort_IT -
    • >>   HAL_UART_AbortReceiveCpltCallback -
    - -

    HAL_UART_IRQHandler (Thumb, 312 bytes, Stack size 8 bytes, stm32f1xx_hal_uart.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_DMA_Abort_IT -
    • >>   HAL_UART_ErrorCallback -
    • >>   UART_Receive_IT -
    • >>   UART_Transmit_IT -
    • >>   UART_EndTransmit_IT -
    • >>   UART_EndRxTransfer -
    - -

    HAL_LIN_SendBreak (Thumb, 70 bytes, Stack size 0 bytes, stm32f1xx_hal_uart.o(.text), UNUSED) - -

    HAL_MultiProcessor_EnterMuteMode (Thumb, 50 bytes, Stack size 0 bytes, stm32f1xx_hal_uart.o(.text), UNUSED) - -

    HAL_MultiProcessor_ExitMuteMode (Thumb, 50 bytes, Stack size 0 bytes, stm32f1xx_hal_uart.o(.text), UNUSED) - -

    HAL_HalfDuplex_EnableTransmitter (Thumb, 54 bytes, Stack size 0 bytes, stm32f1xx_hal_uart.o(.text), UNUSED) - -

    HAL_HalfDuplex_EnableReceiver (Thumb, 54 bytes, Stack size 0 bytes, stm32f1xx_hal_uart.o(.text), UNUSED) - -

    HAL_UART_GetState (Thumb, 12 bytes, Stack size 0 bytes, stm32f1xx_hal_uart.o(.text), UNUSED) - -

    HAL_UART_GetError (Thumb, 4 bytes, Stack size 0 bytes, stm32f1xx_hal_uart.o(.text), UNUSED) - -

    __aeabi_memset (Thumb, 14 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED) -

    [Called By]

    • >>   _memset$wrapper -
    • >>   __aeabi_memclr -
    - -

    __aeabi_memset4 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED) - -

    __aeabi_memset8 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED) - -

    __aeabi_memclr (Thumb, 4 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED) -

    [Calls]

    • >>   __aeabi_memset -
    - -

    __aeabi_memclr4 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text)) -

    [Called By]

    • >>   Paint_DrawNum -
    • >>   SystemClock_Config -
    - -

    __aeabi_memclr8 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED) - -

    _memset$wrapper (Thumb, 18 bytes, Stack size 8 bytes, memseta.o(.text), UNUSED) -

    [Calls]

    • >>   __aeabi_memset -
    - -

    __aeabi_uidiv (Thumb, 0 bytes, Stack size 12 bytes, uidiv.o(.text), UNUSED) - -

    __aeabi_uidivmod (Thumb, 44 bytes, Stack size 12 bytes, uidiv.o(.text), UNUSED) -

    [Called By]

    • >>   _printf_core -
    - -

    __scatterload (Thumb, 28 bytes, Stack size 0 bytes, init.o(.text)) -

    [Calls]

    • >>   __main_after_scatterload -
    -
    [Called By]
    • >>   _main_scatterload -
    - -

    __scatterload_rt2 (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED) - -

    __0printf$3 (Thumb, 22 bytes, Stack size 24 bytes, printf3.o(i.__0printf$3), UNUSED) -

    [Calls]

    • >>   _printf_core -
    - -

    __1printf$3 (Thumb, 0 bytes, Stack size 24 bytes, printf3.o(i.__0printf$3), UNUSED) - -

    __2printf (Thumb, 0 bytes, Stack size 24 bytes, printf3.o(i.__0printf$3)) -

    [Stack]

    • Max Depth = 24
    • Call Chain = __2printf -
    -
    [Called By]
    • >>   Paint_SetScale -
    • >>   Paint_DrawString_EN -
    • >>   Paint_DrawRectangle -
    • >>   Paint_DrawPoint -
    • >>   Paint_DrawNum -
    • >>   Paint_DrawLine -
    • >>   Paint_DrawCircle -
    • >>   HardFault_Handler -
    • >>   EPD_2in36g_test -
    • >>   Error_Handler -
    • >>   Paint_SetMirroring -
    • >>   Paint_DrawChar -
    • >>   Paint_SetPixel -
    • >>   Paint_SetRotate -
    • >>   EPD_2IN36G_ReadBusyH -
    - -

    __scatterload_copy (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED) - -

    __scatterload_null (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED) - -

    __scatterload_zeroinit (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED) - -

    free (Thumb, 76 bytes, Stack size 8 bytes, malloc.o(i.free)) -

    [Stack]

    • Max Depth = 8
    • Call Chain = free -
    -
    [Called By]
    • >>   EPD_2in36g_test -
    - -

    malloc (Thumb, 92 bytes, Stack size 20 bytes, malloc.o(i.malloc)) -

    [Stack]

    • Max Depth = 20
    • Call Chain = malloc -
    -
    [Called By]
    • >>   EPD_2in36g_test -
    -

    -

    -Local Symbols -

    -

    EPD_2IN36G_ReadBusyH (Thumb, 40 bytes, Stack size 8 bytes, epd_2in36g.o(.text)) -

    [Stack]

    • Max Depth = 32
    • Call Chain = EPD_2IN36G_ReadBusyH ⇒ __2printf -
    -
    [Calls]
    • >>   HAL_Delay -
    • >>   HAL_GPIO_ReadPin -
    • >>   __2printf -
    -
    [Called By]
    • >>   EPD_2IN36G_Display -
    • >>   EPD_2IN36G_Clear -
    • >>   EPD_2IN36G_TurnOnDisplay -
    - -

    EPD_2IN36G_SendCommand (Thumb, 46 bytes, Stack size 16 bytes, epd_2in36g.o(.text)) -

    [Stack]

    • Max Depth = 112
    • Call Chain = EPD_2IN36G_SendCommand ⇒ DEV_SPI_WriteByte ⇒ HAL_SPI_Transmit ⇒ SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout -
    -
    [Calls]
    • >>   HAL_GPIO_WritePin -
    • >>   DEV_SPI_WriteByte -
    -
    [Called By]
    • >>   EPD_2IN36G_Sleep -
    • >>   EPD_2IN36G_Init -
    • >>   EPD_2IN36G_Display -
    • >>   EPD_2IN36G_Clear -
    • >>   EPD_2IN36G_TurnOnDisplay -
    - -

    EPD_2IN36G_SendData (Thumb, 46 bytes, Stack size 16 bytes, epd_2in36g.o(.text)) -

    [Stack]

    • Max Depth = 112
    • Call Chain = EPD_2IN36G_SendData ⇒ DEV_SPI_WriteByte ⇒ HAL_SPI_Transmit ⇒ SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout -
    -
    [Calls]
    • >>   HAL_GPIO_WritePin -
    • >>   DEV_SPI_WriteByte -
    -
    [Called By]
    • >>   EPD_2IN36G_Sleep -
    • >>   EPD_2IN36G_Init -
    • >>   EPD_2IN36G_Display -
    • >>   EPD_2IN36G_Clear -
    • >>   EPD_2IN36G_TurnOnDisplay -
    - -

    EPD_2IN36G_TurnOnDisplay (Thumb, 36 bytes, Stack size 8 bytes, epd_2in36g.o(.text)) -

    [Stack]

    • Max Depth = 120
    • Call Chain = EPD_2IN36G_TurnOnDisplay ⇒ EPD_2IN36G_SendData ⇒ DEV_SPI_WriteByte ⇒ HAL_SPI_Transmit ⇒ SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout -
    -
    [Calls]
    • >>   EPD_2IN36G_SendData -
    • >>   EPD_2IN36G_SendCommand -
    • >>   EPD_2IN36G_ReadBusyH -
    -
    [Called By]
    • >>   EPD_2IN36G_Display -
    • >>   EPD_2IN36G_Clear -
    - -

    SPI_WaitFlagStateUntilTimeout (Thumb, 210 bytes, Stack size 32 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Stack]

    • Max Depth = 32
    • Call Chain = SPI_WaitFlagStateUntilTimeout -
    -
    [Calls]
    • >>   HAL_GetTick -
    -
    [Called By]
    • >>   SPI_EndRxTransaction -
    • >>   SPI_EndRxTxTransaction -
    - -

    SPI_EndRxTxTransaction (Thumb, 36 bytes, Stack size 16 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Stack]

    • Max Depth = 48
    • Call Chain = SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout -
    -
    [Calls]
    • >>   SPI_WaitFlagStateUntilTimeout -
    -
    [Called By]
    • >>   HAL_SPI_TransmitReceive -
    • >>   SPI_DMARxAbortCallback -
    • >>   SPI_DMATransmitReceiveCplt -
    • >>   SPI_DMATransmitCplt -
    • >>   SPI_CloseRxTx_ISR -
    • >>   SPI_CloseTx_ISR -
    • >>   HAL_SPI_Transmit -
    - -

    SPI_EndRxTransaction (Thumb, 112 bytes, Stack size 16 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Stack]

    • Max Depth = 48
    • Call Chain = SPI_EndRxTransaction ⇒ SPI_WaitFlagStateUntilTimeout -
    -
    [Calls]
    • >>   SPI_WaitFlagStateUntilTimeout -
    -
    [Called By]
    • >>   HAL_SPI_Receive -
    • >>   SPI_DMAReceiveCplt -
    • >>   SPI_CloseRx_ISR -
    - -

    SPI_CloseTx_ISR (Thumb, 130 bytes, Stack size 16 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Stack]

    • Max Depth = 64
    • Call Chain = SPI_CloseTx_ISR ⇒ SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout -
    -
    [Calls]
    • >>   HAL_SPI_ErrorCallback -
    • >>   HAL_SPI_TxCpltCallback -
    • >>   HAL_GetTick -
    • >>   SPI_EndRxTxTransaction -
    -
    [Called By]
    • >>   SPI_TxISR_16BIT -
    • >>   SPI_TxISR_8BIT -
    - -

    SPI_TxISR_8BIT (Thumb, 30 bytes, Stack size 0 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Stack]

    • Max Depth = 64
    • Call Chain = SPI_TxISR_8BIT ⇒ SPI_CloseTx_ISR ⇒ SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout -
    -
    [Calls]
    • >>   SPI_CloseTx_ISR -
    -
    [Address Reference Count : 1]
    • stm32f1xx_hal_spi.o(.text) -
    -

    SPI_TxISR_16BIT (Thumb, 30 bytes, Stack size 0 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Stack]

    • Max Depth = 64
    • Call Chain = SPI_TxISR_16BIT ⇒ SPI_CloseTx_ISR ⇒ SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout -
    -
    [Calls]
    • >>   SPI_CloseTx_ISR -
    -
    [Address Reference Count : 1]
    • stm32f1xx_hal_spi.o(.text) -
    -

    SPI_CloseRx_ISR (Thumb, 76 bytes, Stack size 16 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Stack]

    • Max Depth = 64
    • Call Chain = SPI_CloseRx_ISR ⇒ SPI_EndRxTransaction ⇒ SPI_WaitFlagStateUntilTimeout -
    -
    [Calls]
    • >>   HAL_SPI_RxCpltCallback -
    • >>   HAL_SPI_ErrorCallback -
    • >>   HAL_GetTick -
    • >>   SPI_EndRxTransaction -
    -
    [Called By]
    • >>   SPI_RxISR_16BIT -
    • >>   SPI_RxISR_8BIT -
    - -

    SPI_RxISR_8BIT (Thumb, 30 bytes, Stack size 0 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Stack]

    • Max Depth = 64
    • Call Chain = SPI_RxISR_8BIT ⇒ SPI_CloseRx_ISR ⇒ SPI_EndRxTransaction ⇒ SPI_WaitFlagStateUntilTimeout -
    -
    [Calls]
    • >>   SPI_CloseRx_ISR -
    -
    [Address Reference Count : 1]
    • stm32f1xx_hal_spi.o(.text) -
    -

    SPI_RxISR_16BIT (Thumb, 30 bytes, Stack size 0 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Stack]

    • Max Depth = 64
    • Call Chain = SPI_RxISR_16BIT ⇒ SPI_CloseRx_ISR ⇒ SPI_EndRxTransaction ⇒ SPI_WaitFlagStateUntilTimeout -
    -
    [Calls]
    • >>   SPI_CloseRx_ISR -
    -
    [Address Reference Count : 1]
    • stm32f1xx_hal_spi.o(.text) -
    -

    SPI_CloseRxTx_ISR (Thumb, 158 bytes, Stack size 16 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Stack]

    • Max Depth = 64
    • Call Chain = SPI_CloseRxTx_ISR ⇒ SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout -
    -
    [Calls]
    • >>   HAL_SPI_TxRxCpltCallback -
    • >>   HAL_SPI_RxCpltCallback -
    • >>   HAL_SPI_ErrorCallback -
    • >>   HAL_GetTick -
    • >>   SPI_EndRxTxTransaction -
    -
    [Called By]
    • >>   SPI_2linesRxISR_16BIT -
    • >>   SPI_2linesTxISR_16BIT -
    • >>   SPI_2linesRxISR_8BIT -
    • >>   SPI_2linesTxISR_8BIT -
    - -

    SPI_2linesTxISR_8BIT (Thumb, 46 bytes, Stack size 0 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Stack]

    • Max Depth = 64
    • Call Chain = SPI_2linesTxISR_8BIT ⇒ SPI_CloseRxTx_ISR ⇒ SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout -
    -
    [Calls]
    • >>   SPI_CloseRxTx_ISR -
    -
    [Address Reference Count : 1]
    • stm32f1xx_hal_spi.o(.text) -
    -

    SPI_2linesRxISR_8BIT (Thumb, 46 bytes, Stack size 0 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Stack]

    • Max Depth = 64
    • Call Chain = SPI_2linesRxISR_8BIT ⇒ SPI_CloseRxTx_ISR ⇒ SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout -
    -
    [Calls]
    • >>   SPI_CloseRxTx_ISR -
    -
    [Address Reference Count : 1]
    • stm32f1xx_hal_spi.o(.text) -
    -

    SPI_2linesTxISR_16BIT (Thumb, 46 bytes, Stack size 0 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Stack]

    • Max Depth = 64
    • Call Chain = SPI_2linesTxISR_16BIT ⇒ SPI_CloseRxTx_ISR ⇒ SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout -
    -
    [Calls]
    • >>   SPI_CloseRxTx_ISR -
    -
    [Address Reference Count : 1]
    • stm32f1xx_hal_spi.o(.text) -
    -

    SPI_2linesRxISR_16BIT (Thumb, 46 bytes, Stack size 0 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Stack]

    • Max Depth = 64
    • Call Chain = SPI_2linesRxISR_16BIT ⇒ SPI_CloseRxTx_ISR ⇒ SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout -
    -
    [Calls]
    • >>   SPI_CloseRxTx_ISR -
    -
    [Address Reference Count : 1]
    • stm32f1xx_hal_spi.o(.text) -
    -

    SPI_DMAError (Thumb, 34 bytes, Stack size 8 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Stack]

    • Max Depth = 8
    • Call Chain = SPI_DMAError -
    -
    [Calls]
    • >>   HAL_SPI_ErrorCallback -
    -
    [Address Reference Count : 1]
    • stm32f1xx_hal_spi.o(.text) -
    -

    SPI_DMATransmitCplt (Thumb, 102 bytes, Stack size 16 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Stack]

    • Max Depth = 64
    • Call Chain = SPI_DMATransmitCplt ⇒ SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout -
    -
    [Calls]
    • >>   HAL_SPI_ErrorCallback -
    • >>   HAL_SPI_TxCpltCallback -
    • >>   HAL_GetTick -
    • >>   SPI_EndRxTxTransaction -
    -
    [Address Reference Count : 1]
    • stm32f1xx_hal_spi.o(.text) -
    -

    SPI_DMAHalfTransmitCplt (Thumb, 10 bytes, Stack size 8 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Stack]

    • Max Depth = 8
    • Call Chain = SPI_DMAHalfTransmitCplt -
    -
    [Calls]
    • >>   HAL_SPI_TxHalfCpltCallback -
    -
    [Address Reference Count : 1]
    • stm32f1xx_hal_spi.o(.text) -
    -

    SPI_DMAReceiveCplt (Thumb, 110 bytes, Stack size 16 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Stack]

    • Max Depth = 64
    • Call Chain = SPI_DMAReceiveCplt ⇒ SPI_EndRxTransaction ⇒ SPI_WaitFlagStateUntilTimeout -
    -
    [Calls]
    • >>   HAL_SPI_RxCpltCallback -
    • >>   HAL_SPI_ErrorCallback -
    • >>   HAL_GetTick -
    • >>   SPI_EndRxTransaction -
    -
    [Address Reference Count : 1]
    • stm32f1xx_hal_spi.o(.text) -
    -

    SPI_DMAHalfReceiveCplt (Thumb, 10 bytes, Stack size 8 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Stack]

    • Max Depth = 8
    • Call Chain = SPI_DMAHalfReceiveCplt -
    -
    [Calls]
    • >>   HAL_SPI_RxHalfCpltCallback -
    -
    [Address Reference Count : 1]
    • stm32f1xx_hal_spi.o(.text) -
    -

    SPI_DMATransmitReceiveCplt (Thumb, 92 bytes, Stack size 16 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Stack]

    • Max Depth = 64
    • Call Chain = SPI_DMATransmitReceiveCplt ⇒ SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout -
    -
    [Calls]
    • >>   HAL_SPI_TxRxCpltCallback -
    • >>   HAL_SPI_ErrorCallback -
    • >>   HAL_GetTick -
    • >>   SPI_EndRxTxTransaction -
    -
    [Address Reference Count : 1]
    • stm32f1xx_hal_spi.o(.text) -
    -

    SPI_DMAHalfTransmitReceiveCplt (Thumb, 10 bytes, Stack size 8 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Stack]

    • Max Depth = 8
    • Call Chain = SPI_DMAHalfTransmitReceiveCplt -
    -
    [Calls]
    • >>   HAL_SPI_TxRxHalfCpltCallback -
    -
    [Address Reference Count : 1]
    • stm32f1xx_hal_spi.o(.text) -
    -

    SPI_AbortRx_ISR (Thumb, 82 bytes, Stack size 4 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Stack]

    • Max Depth = 4
    • Call Chain = SPI_AbortRx_ISR -
    -
    [Address Reference Count : 1]
    • stm32f1xx_hal_spi.o(.text) -
    -

    SPI_AbortTx_ISR (Thumb, 28 bytes, Stack size 0 bytes, stm32f1xx_hal_spi.o(.text)) -
    [Address Reference Count : 1]

    • stm32f1xx_hal_spi.o(.text) -
    -

    SPI_DMARxAbortCallback (Thumb, 98 bytes, Stack size 16 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Stack]

    • Max Depth = 64
    • Call Chain = SPI_DMARxAbortCallback ⇒ SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout -
    -
    [Calls]
    • >>   HAL_SPI_AbortCpltCallback -
    • >>   HAL_GetTick -
    • >>   SPI_EndRxTxTransaction -
    -
    [Address Reference Count : 1]
    • stm32f1xx_hal_spi.o(.text) -
    -

    SPI_DMATxAbortCallback (Thumb, 114 bytes, Stack size 16 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Stack]

    • Max Depth = 16
    • Call Chain = SPI_DMATxAbortCallback -
    -
    [Calls]
    • >>   HAL_SPI_AbortCpltCallback -
    -
    [Address Reference Count : 1]
    • stm32f1xx_hal_spi.o(.text) -
    -

    SPI_DMAAbortOnError (Thumb, 16 bytes, Stack size 8 bytes, stm32f1xx_hal_spi.o(.text)) -

    [Stack]

    • Max Depth = 8
    • Call Chain = SPI_DMAAbortOnError -
    -
    [Calls]
    • >>   HAL_SPI_ErrorCallback -
    -
    [Address Reference Count : 1]
    • stm32f1xx_hal_spi.o(.text) -
    -

    RCC_Delay (Thumb, 32 bytes, Stack size 4 bytes, stm32f1xx_hal_rcc.o(.text)) -

    [Stack]

    • Max Depth = 4
    • Call Chain = RCC_Delay -
    -
    [Called By]
    • >>   HAL_RCC_OscConfig -
    - -

    DMA_SetConfig (Thumb, 56 bytes, Stack size 4 bytes, stm32f1xx_hal_dma.o(.text), UNUSED) -

    [Called By]

    • >>   HAL_DMA_Start -
    • >>   HAL_DMA_Start_IT -
    - -

    UART_SetConfig (Thumb, 194 bytes, Stack size 16 bytes, stm32f1xx_hal_uart.o(.text)) -

    [Stack]

    • Max Depth = 20
    • Call Chain = UART_SetConfig ⇒ HAL_RCC_GetPCLK2Freq -
    -
    [Calls]
    • >>   HAL_RCC_GetPCLK2Freq -
    • >>   HAL_RCC_GetPCLK1Freq -
    -
    [Called By]
    • >>   HAL_UART_Init -
    • >>   HAL_MultiProcessor_Init -
    • >>   HAL_LIN_Init -
    • >>   HAL_HalfDuplex_Init -
    - -

    UART_WaitOnFlagUntilTimeout (Thumb, 120 bytes, Stack size 24 bytes, stm32f1xx_hal_uart.o(.text)) -

    [Stack]

    • Max Depth = 24
    • Call Chain = UART_WaitOnFlagUntilTimeout -
    -
    [Calls]
    • >>   HAL_GetTick -
    -
    [Called By]
    • >>   HAL_UART_Transmit -
    • >>   HAL_UART_Receive -
    - -

    UART_EndRxTransfer (Thumb, 28 bytes, Stack size 0 bytes, stm32f1xx_hal_uart.o(.text)) -

    [Called By]

    • >>   HAL_UART_IRQHandler -
    • >>   HAL_UART_DMAStop -
    • >>   UART_DMAError -
    - -

    UART_EndTxTransfer (Thumb, 18 bytes, Stack size 0 bytes, stm32f1xx_hal_uart.o(.text)) -

    [Called By]

    • >>   HAL_UART_DMAStop -
    • >>   UART_DMAError -
    - -

    UART_DMAError (Thumb, 74 bytes, Stack size 16 bytes, stm32f1xx_hal_uart.o(.text)) -

    [Stack]

    • Max Depth = 16
    • Call Chain = UART_DMAError -
    -
    [Calls]
    • >>   HAL_UART_ErrorCallback -
    • >>   UART_EndTxTransfer -
    • >>   UART_EndRxTransfer -
    -
    [Address Reference Count : 1]
    • stm32f1xx_hal_uart.o(.text) -
    -

    UART_DMATxHalfCplt (Thumb, 10 bytes, Stack size 8 bytes, stm32f1xx_hal_uart.o(.text)) -

    [Stack]

    • Max Depth = 8
    • Call Chain = UART_DMATxHalfCplt -
    -
    [Calls]
    • >>   HAL_UART_TxHalfCpltCallback -
    -
    [Address Reference Count : 1]
    • stm32f1xx_hal_uart.o(.text) -
    -

    UART_DMATransmitCplt (Thumb, 48 bytes, Stack size 8 bytes, stm32f1xx_hal_uart.o(.text)) -

    [Stack]

    • Max Depth = 8
    • Call Chain = UART_DMATransmitCplt -
    -
    [Calls]
    • >>   HAL_UART_TxCpltCallback -
    -
    [Address Reference Count : 1]
    • stm32f1xx_hal_uart.o(.text) -
    -

    UART_DMARxHalfCplt (Thumb, 10 bytes, Stack size 8 bytes, stm32f1xx_hal_uart.o(.text)) -

    [Stack]

    • Max Depth = 8
    • Call Chain = UART_DMARxHalfCplt -
    -
    [Calls]
    • >>   HAL_UART_RxHalfCpltCallback -
    -
    [Address Reference Count : 1]
    • stm32f1xx_hal_uart.o(.text) -
    -

    UART_DMAReceiveCplt (Thumb, 62 bytes, Stack size 8 bytes, stm32f1xx_hal_uart.o(.text)) -

    [Stack]

    • Max Depth = 8
    • Call Chain = UART_DMAReceiveCplt -
    -
    [Calls]
    • >>   HAL_UART_RxCpltCallback -
    -
    [Address Reference Count : 1]
    • stm32f1xx_hal_uart.o(.text) -
    -

    UART_DMARxAbortCallback (Thumb, 44 bytes, Stack size 8 bytes, stm32f1xx_hal_uart.o(.text)) -

    [Stack]

    • Max Depth = 8
    • Call Chain = UART_DMARxAbortCallback -
    -
    [Calls]
    • >>   HAL_UART_AbortCpltCallback -
    -
    [Address Reference Count : 1]
    • stm32f1xx_hal_uart.o(.text) -
    -

    UART_DMATxAbortCallback (Thumb, 66 bytes, Stack size 8 bytes, stm32f1xx_hal_uart.o(.text)) -

    [Stack]

    • Max Depth = 8
    • Call Chain = UART_DMATxAbortCallback -
    -
    [Calls]
    • >>   HAL_UART_AbortCpltCallback -
    -
    [Address Reference Count : 1]
    • stm32f1xx_hal_uart.o(.text) -
    -

    UART_DMATxOnlyAbortCallback (Thumb, 20 bytes, Stack size 8 bytes, stm32f1xx_hal_uart.o(.text)) -

    [Stack]

    • Max Depth = 8
    • Call Chain = UART_DMATxOnlyAbortCallback -
    -
    [Calls]
    • >>   HAL_UART_AbortTransmitCpltCallback -
    -
    [Address Reference Count : 1]
    • stm32f1xx_hal_uart.o(.text) -
    -

    UART_DMARxOnlyAbortCallback (Thumb, 20 bytes, Stack size 8 bytes, stm32f1xx_hal_uart.o(.text)) -

    [Stack]

    • Max Depth = 8
    • Call Chain = UART_DMARxOnlyAbortCallback -
    -
    [Calls]
    • >>   HAL_UART_AbortReceiveCpltCallback -
    -
    [Address Reference Count : 1]
    • stm32f1xx_hal_uart.o(.text) -
    -

    UART_EndTransmit_IT (Thumb, 26 bytes, Stack size 8 bytes, stm32f1xx_hal_uart.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_UART_TxCpltCallback -
    -
    [Called By]
    • >>   HAL_UART_IRQHandler -
    - -

    UART_Transmit_IT (Thumb, 94 bytes, Stack size 0 bytes, stm32f1xx_hal_uart.o(.text), UNUSED) -

    [Called By]

    • >>   HAL_UART_IRQHandler -
    - -

    UART_DMAAbortOnError (Thumb, 16 bytes, Stack size 8 bytes, stm32f1xx_hal_uart.o(.text)) -

    [Stack]

    • Max Depth = 8
    • Call Chain = UART_DMAAbortOnError -
    -
    [Calls]
    • >>   HAL_UART_ErrorCallback -
    -
    [Address Reference Count : 1]
    • stm32f1xx_hal_uart.o(.text) -
    -

    UART_Receive_IT (Thumb, 146 bytes, Stack size 8 bytes, stm32f1xx_hal_uart.o(.text), UNUSED) -

    [Calls]

    • >>   HAL_UART_RxCpltCallback -
    -
    [Called By]
    • >>   HAL_UART_IRQHandler -
    - -

    _printf_core (Thumb, 436 bytes, Stack size 96 bytes, printf3.o(i._printf_core), UNUSED) -

    [Calls]

    • >>   __aeabi_uidivmod -
    -
    [Called By]
    • >>   __0printf$3 -
    -

    -

    -Undefined Global Symbols -


    diff --git a/STM32/STM32-F103ZET6/MDK-ARM/epd-demo/epd-demo.map b/STM32/STM32-F103ZET6/MDK-ARM/epd-demo/epd-demo.map index c5b893f..10ee021 100644 --- a/STM32/STM32-F103ZET6/MDK-ARM/epd-demo/epd-demo.map +++ b/STM32/STM32-F103ZET6/MDK-ARM/epd-demo/epd-demo.map @@ -16,7 +16,7 @@ Section Cross References main.o(.text) refers to gpio.o(.text) for MX_GPIO_Init main.o(.text) refers to usart.o(.text) for MX_USART1_UART_Init main.o(.text) refers to spi.o(.text) for MX_SPI1_Init - main.o(.text) refers to epd_2in36g_test.o(.text) for EPD_2in36g_test + main.o(.text) refers to epd_3in52_test.o(.text) for EPD_test gpio.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_WritePin spi.o(.text) refers to stm32f1xx_hal_spi.o(.text) for HAL_SPI_Init spi.o(.text) refers to main.o(.text) for Error_Handler @@ -28,293 +28,6 @@ Section Cross References usart.o(.text) refers to usart.o(.bss) for .bss stm32f1xx_it.o(.text) refers to printf3.o(i.__0printf$3) for __2printf stm32f1xx_it.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_IncTick - epd_1in02_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_1in02_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_1in02_test.o(.text) refers to epd_1in02d.o(.text) for EPD_1IN02_Init - epd_1in02_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_1in02_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_1in02_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_1in02_test.o(.text) refers to memcpya.o(.text) for __aeabi_memcpy - epd_1in02_test.o(.text) refers to malloc.o(i.free) for free - epd_1in02_test.o(.text) refers to font16.o(.data) for Font16 - epd_1in02_test.o(.text) refers to font12.o(.data) for Font12 - epd_1in02_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_1in02_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_1in02_test.o(.text) refers to font20.o(.data) for Font20 - epd_1in54_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_1in54_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_1in54_test.o(.text) refers to epd_1in54.o(.text) for EPD_1IN54_Init - epd_1in54_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_1in54_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_1in54_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_1in54_test.o(.text) refers to malloc.o(i.free) for free - epd_1in54_test.o(.text) refers to imagedata.o(.constdata) for gImage_1in54 - epd_1in54_test.o(.text) refers to font20.o(.data) for Font20 - epd_1in54_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_1in54_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_1in54_v2_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_1in54_v2_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_1in54_v2_test.o(.text) refers to epd_1in54_v2.o(.text) for EPD_1IN54_V2_Init - epd_1in54_v2_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_1in54_v2_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_1in54_v2_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_1in54_v2_test.o(.text) refers to malloc.o(i.free) for free - epd_1in54_v2_test.o(.text) refers to imagedata.o(.constdata) for gImage_1in54 - epd_1in54_v2_test.o(.text) refers to font20.o(.data) for Font20 - epd_1in54_v2_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_1in54_v2_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_1in54b_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_1in54b_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_1in54b_test.o(.text) refers to epd_1in54b.o(.text) for EPD_1IN54B_Init - epd_1in54b_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_1in54b_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_1in54b_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_1in54b_test.o(.text) refers to malloc.o(i.free) for free - epd_1in54b_test.o(.text) refers to font16.o(.data) for Font16 - epd_1in54b_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_1in54b_test.o(.text) refers to font20.o(.data) for Font20 - epd_1in54b_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_1in54b_test.o(.text) refers to imagedata.o(.constdata) for gImage_1in54b_Black - epd_1in54b_test.o(.text) refers to imagedata.o(.constdata) for gImage_1in54b_Red - epd_1in54b_v2_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_1in54b_v2_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_1in54b_v2_test.o(.text) refers to epd_1in54b_v2.o(.text) for EPD_1IN54B_V2_Init - epd_1in54b_v2_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_1in54b_v2_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_1in54b_v2_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_1in54b_v2_test.o(.text) refers to malloc.o(i.free) for free - epd_1in54b_v2_test.o(.text) refers to font16.o(.data) for Font16 - epd_1in54b_v2_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_1in54b_v2_test.o(.text) refers to font20.o(.data) for Font20 - epd_1in54b_v2_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_1in54b_v2_test.o(.text) refers to imagedata.o(.constdata) for gImage_1in54b_Black - epd_1in54b_v2_test.o(.text) refers to imagedata.o(.constdata) for gImage_1in54b_Red - epd_1in54c_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_1in54c_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_1in54c_test.o(.text) refers to epd_1in54c.o(.text) for EPD_1IN54C_Init - epd_1in54c_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_1in54c_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_1in54c_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_1in54c_test.o(.text) refers to malloc.o(i.free) for free - epd_1in54c_test.o(.text) refers to font20.o(.data) for Font20 - epd_1in54c_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_1in54c_test.o(.text) refers to imagedata.o(.constdata) for gImage_1in54c_Black - epd_1in54c_test.o(.text) refers to imagedata.o(.constdata) for gImage_1in54c_Yellow - epd_2in7_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in7_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_2in7_test.o(.text) refers to epd_2in7.o(.text) for EPD_2IN7_Init - epd_2in7_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in7_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_2in7_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_2in7_test.o(.text) refers to malloc.o(i.free) for free - epd_2in7_test.o(.text) refers to imagedata.o(.constdata) for gImage_2in7 - epd_2in7_test.o(.text) refers to font16.o(.data) for Font16 - epd_2in7_test.o(.text) refers to font12.o(.data) for Font12 - epd_2in7_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_2in7_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_2in7_test.o(.text) refers to imagedata.o(.constdata) for gImage_2in7_4Gray - epd_2in7b_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in7b_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_2in7b_test.o(.text) refers to epd_2in7b.o(.text) for EPD_2IN7B_Init - epd_2in7b_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in7b_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_2in7b_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_2in7b_test.o(.text) refers to malloc.o(i.free) for free - epd_2in7b_test.o(.text) refers to imagedata.o(.constdata) for gImage_2in7b_Black - epd_2in7b_test.o(.text) refers to imagedata.o(.constdata) for gImage_2in7b_Red - epd_2in7b_test.o(.text) refers to font16.o(.data) for Font16 - epd_2in7b_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_2in7b_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_2in7b_test.o(.text) refers to font12.o(.data) for Font12 - epd_2in7b_v2_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in7b_v2_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_2in7b_v2_test.o(.text) refers to epd_2in7b_v2.o(.text) for EPD_2IN7B_V2_Init - epd_2in7b_v2_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in7b_v2_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_2in7b_v2_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_2in7b_v2_test.o(.text) refers to malloc.o(i.free) for free - epd_2in7b_v2_test.o(.text) refers to imagedata.o(.constdata) for gImage_2in7b_Black - epd_2in7b_v2_test.o(.text) refers to imagedata.o(.constdata) for gImage_2in7b_Red - epd_2in7b_v2_test.o(.text) refers to font16.o(.data) for Font16 - epd_2in7b_v2_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_2in7b_v2_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_2in7b_v2_test.o(.text) refers to font12.o(.data) for Font12 - epd_2in9_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in9_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_2in9_test.o(.text) refers to epd_2in9.o(.text) for EPD_2IN9_Init - epd_2in9_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in9_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_2in9_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_2in9_test.o(.text) refers to malloc.o(i.free) for free - epd_2in9_test.o(.text) refers to imagedata.o(.constdata) for gImage_2in9 - epd_2in9_test.o(.text) refers to font16.o(.data) for Font16 - epd_2in9_test.o(.text) refers to font12.o(.data) for Font12 - epd_2in9_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_2in9_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_2in9_test.o(.text) refers to font20.o(.data) for Font20 - epd_2in9_v2_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in9_v2_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_2in9_v2_test.o(.text) refers to epd_2in9_v2.o(.text) for EPD_2IN9_V2_Init - epd_2in9_v2_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_2in9_v2_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_2in9_v2_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in9_v2_test.o(.text) refers to malloc.o(i.free) for free - epd_2in9_v2_test.o(.text) refers to imagedata.o(.constdata) for gImage_2in9 - epd_2in9_v2_test.o(.text) refers to font16.o(.data) for Font16 - epd_2in9_v2_test.o(.text) refers to font12.o(.data) for Font12 - epd_2in9_v2_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_2in9_v2_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_2in9_v2_test.o(.text) refers to font20.o(.data) for Font20 - epd_2in9bc_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in9bc_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_2in9bc_test.o(.text) refers to epd_2in9bc.o(.text) for EPD_2IN9BC_Init - epd_2in9bc_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in9bc_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_2in9bc_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_2in9bc_test.o(.text) refers to malloc.o(i.free) for free - epd_2in9bc_test.o(.text) refers to imagedata.o(.constdata) for gImage_2in9bc_ry - epd_2in9bc_test.o(.text) refers to imagedata.o(.constdata) for gImage_2in9bc_b - epd_2in9bc_test.o(.text) refers to font16.o(.data) for Font16 - epd_2in9bc_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_2in9bc_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_2in9bc_test.o(.text) refers to font12.o(.data) for Font12 - epd_2in9b_v3_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in9b_v3_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_2in9b_v3_test.o(.text) refers to epd_2in9b_v3.o(.text) for EPD_2IN9B_V3_Init - epd_2in9b_v3_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in9b_v3_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_2in9b_v3_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_2in9b_v3_test.o(.text) refers to malloc.o(i.free) for free - epd_2in9b_v3_test.o(.text) refers to imagedata.o(.constdata) for gImage_2in9bc_ry - epd_2in9b_v3_test.o(.text) refers to imagedata.o(.constdata) for gImage_2in9bc_b - epd_2in9b_v3_test.o(.text) refers to font16.o(.data) for Font16 - epd_2in9b_v3_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_2in9b_v3_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_2in9b_v3_test.o(.text) refers to font12.o(.data) for Font12 - epd_2in9d_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in9d_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_2in9d_test.o(.text) refers to epd_2in9d.o(.text) for EPD_2IN9D_Init - epd_2in9d_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in9d_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_2in9d_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_2in9d_test.o(.text) refers to malloc.o(i.free) for free - epd_2in9d_test.o(.text) refers to imagedata.o(.constdata) for gImage_2in9 - epd_2in9d_test.o(.text) refers to font16.o(.data) for Font16 - epd_2in9d_test.o(.text) refers to font12.o(.data) for Font12 - epd_2in9d_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_2in9d_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_2in9d_test.o(.text) refers to font20.o(.data) for Font20 - epd_2in13_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in13_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_2in13_test.o(.text) refers to epd_2in13.o(.text) for EPD_2IN13_Init - epd_2in13_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in13_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_2in13_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_2in13_test.o(.text) refers to malloc.o(i.free) for free - epd_2in13_test.o(.text) refers to imagedata.o(.constdata) for gImage_2in13 - epd_2in13_test.o(.text) refers to font16.o(.data) for Font16 - epd_2in13_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_2in13_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_2in13_test.o(.text) refers to font20.o(.data) for Font20 - epd_2in13_v2_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in13_v2_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_2in13_v2_test.o(.text) refers to epd_2in13_v2.o(.text) for EPD_2IN13_V2_Init - epd_2in13_v2_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in13_v2_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_2in13_v2_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_2in13_v2_test.o(.text) refers to malloc.o(i.free) for free - epd_2in13_v2_test.o(.text) refers to imagedata.o(.constdata) for gImage_2in13 - epd_2in13_v2_test.o(.text) refers to font16.o(.data) for Font16 - epd_2in13_v2_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_2in13_v2_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_2in13_v2_test.o(.text) refers to font20.o(.data) for Font20 - epd_2in13_v3_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in13_v3_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_2in13_v3_test.o(.text) refers to epd_2in13_v3.o(.text) for EPD_2in13_V3_Init - epd_2in13_v3_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_2in13_v3_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_2in13_v3_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in13_v3_test.o(.text) refers to malloc.o(i.free) for free - epd_2in13_v3_test.o(.text) refers to imagedata.o(.constdata) for gImage_2in13 - epd_2in13_v3_test.o(.text) refers to font16.o(.data) for Font16 - epd_2in13_v3_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_2in13_v3_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_2in13_v3_test.o(.text) refers to font20.o(.data) for Font20 - epd_2in13b_v3_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in13b_v3_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_2in13b_v3_test.o(.text) refers to epd_2in13b_v3.o(.text) for EPD_2IN13B_V3_Init - epd_2in13b_v3_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in13b_v3_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_2in13b_v3_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_2in13b_v3_test.o(.text) refers to malloc.o(i.free) for free - epd_2in13b_v3_test.o(.text) refers to imagedata.o(.constdata) for gImage_2in13c_y - epd_2in13b_v3_test.o(.text) refers to imagedata.o(.constdata) for gImage_2in13c_b - epd_2in13b_v3_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_2in13b_v3_test.o(.text) refers to font12.o(.data) for Font12 - epd_2in13b_v3_test.o(.text) refers to font16.o(.data) for Font16 - epd_2in13b_v4_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in13b_v4_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_2in13b_v4_test.o(.text) refers to epd_2in13b_v4.o(.text) for EPD_2IN13B_V4_Init - epd_2in13b_v4_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in13b_v4_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_2in13b_v4_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_2in13b_v4_test.o(.text) refers to malloc.o(i.free) for free - epd_2in13b_v4_test.o(.text) refers to imagedata2.o(.constdata) for gImage_2in13b_V4r - epd_2in13b_v4_test.o(.text) refers to imagedata2.o(.constdata) for gImage_2in13b_V4b - epd_2in13b_v4_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_2in13b_v4_test.o(.text) refers to font12.o(.data) for Font12 - epd_2in13b_v4_test.o(.text) refers to font16.o(.data) for Font16 - epd_2in13bc_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in13bc_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_2in13bc_test.o(.text) refers to epd_2in13bc.o(.text) for EPD_2IN13BC_Init - epd_2in13bc_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in13bc_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_2in13bc_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_2in13bc_test.o(.text) refers to malloc.o(i.free) for free - epd_2in13bc_test.o(.text) refers to imagedata.o(.constdata) for gImage_2in13c_y - epd_2in13bc_test.o(.text) refers to imagedata.o(.constdata) for gImage_2in13c_b - epd_2in13bc_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_2in13bc_test.o(.text) refers to font12.o(.data) for Font12 - epd_2in13bc_test.o(.text) refers to font16.o(.data) for Font16 - epd_2in13d_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in13d_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_2in13d_test.o(.text) refers to epd_2in13d.o(.text) for EPD_2IN13D_Init - epd_2in13d_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in13d_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_2in13d_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_2in13d_test.o(.text) refers to malloc.o(i.free) for free - epd_2in13d_test.o(.text) refers to imagedata.o(.constdata) for gImage_2in13d - epd_2in13d_test.o(.text) refers to font16.o(.data) for Font16 - epd_2in13d_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_2in13d_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_2in13d_test.o(.text) refers to font20.o(.data) for Font20 - epd_2in66_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in66_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_2in66_test.o(.text) refers to epd_2in66.o(.text) for EPD_2IN66_Init - epd_2in66_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in66_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_2in66_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_2in66_test.o(.text) refers to malloc.o(i.free) for free - epd_2in66_test.o(.text) refers to imagedata.o(.constdata) for gImage_2in66 - epd_2in66_test.o(.text) refers to imagedata.o(.constdata) for gImage_100X50 - epd_2in66_test.o(.text) refers to font16.o(.data) for Font16 - epd_2in66_test.o(.text) refers to font12.o(.data) for Font12 - epd_2in66_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_2in66_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_2in66_test.o(.text) refers to font20.o(.data) for Font20 - epd_2in66b_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in66b_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_2in66b_test.o(.text) refers to epd_2in66b.o(.text) for EPD_2IN66B_Init - epd_2in66b_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in66b_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_2in66b_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_2in66b_test.o(.text) refers to malloc.o(i.free) for free - epd_2in66b_test.o(.text) refers to imagedata.o(.constdata) for gImage_2in66bb - epd_2in66b_test.o(.text) refers to imagedata.o(.constdata) for gImage_2in66br - epd_2in66b_test.o(.text) refers to font16.o(.data) for Font16 - epd_2in66b_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_2in66b_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_2in66b_test.o(.text) refers to font12.o(.data) for Font12 epd_3in52_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf epd_3in52_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init epd_3in52_test.o(.text) refers to epd_3in52.o(.text) for EPD_3IN52_Init @@ -325,458 +38,12 @@ Section Cross References epd_3in52_test.o(.text) refers to imagedata.o(.constdata) for gImage_3in52 epd_3in52_test.o(.text) refers to font16.o(.data) for Font16 epd_3in52_test.o(.text) refers to font12.o(.data) for Font12 - epd_3in7_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_3in7_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_3in7_test.o(.text) refers to epd_3in7.o(.text) for EPD_3IN7_4Gray_Init - epd_3in7_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_3in7_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_3in7_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_3in7_test.o(.text) refers to malloc.o(i.free) for free - epd_3in7_test.o(.text) refers to imagedata.o(.constdata) for gImage_3in7 - epd_3in7_test.o(.text) refers to font16.o(.data) for Font16 - epd_3in7_test.o(.text) refers to font12.o(.data) for Font12 - epd_3in7_test.o(.text) refers to font24.o(.data) for Font24 - epd_3in7_test.o(.text) refers to font20.o(.data) for Font20 - epd_4in01f_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_4in01f_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_4in01f_test.o(.text) refers to epd_4in01f.o(.text) for EPD_4IN01F_Init - epd_4in01f_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_4in01f_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_4in01f_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_4in01f_test.o(.text) refers to malloc.o(i.free) for free - epd_4in01f_test.o(.text) refers to imagedata.o(.constdata) for gImage_4in01 - epd_4in01f_test.o(.text) refers to font16.o(.data) for Font16 - epd_4in01f_test.o(.text) refers to font12.o(.data) for Font12 - epd_4in01f_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_4in01f_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_4in2_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_4in2_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_4in2_test.o(.text) refers to epd_4in2.o(.text) for EPD_4IN2_Init_Fast - epd_4in2_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_4in2_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_4in2_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_4in2_test.o(.text) refers to malloc.o(i.free) for free - epd_4in2_test.o(.text) refers to imagedata.o(.constdata) for gImage_4in2 - epd_4in2_test.o(.text) refers to font16.o(.data) for Font16 - epd_4in2_test.o(.text) refers to font12.o(.data) for Font12 - epd_4in2_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_4in2_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_4in2_test.o(.text) refers to epd_4in2_test.o(.conststring) for .conststring - epd_4in2_test.o(.text) refers to imagedata.o(.constdata) for gImage_4in2_4Gray - epd_4in2bc_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_4in2bc_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_4in2bc_test.o(.text) refers to epd_4in2bc.o(.text) for EPD_4IN2BC_Init - epd_4in2bc_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_4in2bc_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_4in2bc_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_4in2bc_test.o(.text) refers to malloc.o(i.free) for free - epd_4in2bc_test.o(.text) refers to imagedata.o(.constdata) for gImage_4in2bc_ry - epd_4in2bc_test.o(.text) refers to imagedata.o(.constdata) for gImage_4in2bc_b - epd_4in2bc_test.o(.text) refers to font16.o(.data) for Font16 - epd_4in2bc_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_4in2bc_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_4in2bc_test.o(.text) refers to font12.o(.data) for Font12 - epd_4in2b_v2_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_4in2b_v2_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_4in2b_v2_test.o(.text) refers to epd_4in2b_v2.o(.text) for EPD_4IN2B_V2_Init - epd_4in2b_v2_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_4in2b_v2_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_4in2b_v2_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_4in2b_v2_test.o(.text) refers to malloc.o(i.free) for free - epd_4in2b_v2_test.o(.text) refers to imagedata.o(.constdata) for gImage_4in2bc_ry - epd_4in2b_v2_test.o(.text) refers to imagedata.o(.constdata) for gImage_4in2bc_b - epd_4in2b_v2_test.o(.text) refers to font16.o(.data) for Font16 - epd_4in2b_v2_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_4in2b_v2_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_4in2b_v2_test.o(.text) refers to font12.o(.data) for Font12 - epd_5in65f_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_5in65f_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_5in65f_test.o(.text) refers to epd_5in65f.o(.text) for EPD_5IN65F_Init - epd_5in65f_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_5in65f_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_5in65f_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_5in65f_test.o(.text) refers to malloc.o(i.free) for free - epd_5in65f_test.o(.text) refers to font16.o(.data) for Font16 - epd_5in65f_test.o(.text) refers to font12.o(.data) for Font12 - epd_5in65f_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_5in65f_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_5in83_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_5in83_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_5in83_test.o(.text) refers to epd_5in83.o(.text) for EPD_5IN83_Init - epd_5in83_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_5in83_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_5in83_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_5in83_test.o(.text) refers to malloc.o(i.free) for free - epd_5in83_test.o(.text) refers to imagedata.o(.constdata) for gImage_5in83 - epd_5in83_test.o(.text) refers to font16.o(.data) for Font16 - epd_5in83_test.o(.text) refers to font12.o(.data) for Font12 - epd_5in83_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_5in83_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_5in83_v2_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_5in83_v2_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_5in83_v2_test.o(.text) refers to epd_5in83_v2.o(.text) for EPD_5in83_V2_Init - epd_5in83_v2_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_5in83_v2_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_5in83_v2_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_5in83_v2_test.o(.text) refers to malloc.o(i.free) for free - epd_5in83_v2_test.o(.text) refers to imagedata.o(.constdata) for gImage_5in83_V2 - epd_5in83_v2_test.o(.text) refers to font16.o(.data) for Font16 - epd_5in83_v2_test.o(.text) refers to font12.o(.data) for Font12 - epd_5in83_v2_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_5in83_v2_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_5in83bc_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_5in83bc_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_5in83bc_test.o(.text) refers to epd_5in83bc.o(.text) for EPD_5IN83BC_Init - epd_5in83bc_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_5in83bc_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_5in83bc_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_5in83bc_test.o(.text) refers to malloc.o(i.free) for free - epd_5in83bc_test.o(.text) refers to imagedata.o(.constdata) for gImage_5in83bc_ry - epd_5in83bc_test.o(.text) refers to imagedata.o(.constdata) for gImage_5in83bc_b - epd_5in83bc_test.o(.text) refers to font16.o(.data) for Font16 - epd_5in83bc_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_5in83bc_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_5in83bc_test.o(.text) refers to font12.o(.data) for Font12 - epd_5in83b_v2_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_5in83b_v2_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_5in83b_v2_test.o(.text) refers to epd_5in83b_v2.o(.text) for EPD_5IN83B_V2_Init - epd_5in83b_v2_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_5in83b_v2_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_5in83b_v2_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_5in83b_v2_test.o(.text) refers to malloc.o(i.free) for free - epd_5in83b_v2_test.o(.text) refers to imagedata.o(.constdata) for gImage_5in83b_V2_r - epd_5in83b_v2_test.o(.text) refers to imagedata.o(.constdata) for gImage_5in83b_V2_b - epd_5in83b_v2_test.o(.text) refers to font16.o(.data) for Font16 - epd_5in83b_v2_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_5in83b_v2_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_5in83b_v2_test.o(.text) refers to font12.o(.data) for Font12 - epd_7in5_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_7in5_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_7in5_test.o(.text) refers to epd_7in5.o(.text) for EPD_7IN5_Init - epd_7in5_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_7in5_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_7in5_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_7in5_test.o(.text) refers to malloc.o(i.free) for free - epd_7in5_test.o(.text) refers to imagedata.o(.constdata) for gImage_7in5 - epd_7in5_test.o(.text) refers to font16.o(.data) for Font16 - epd_7in5_test.o(.text) refers to font12.o(.data) for Font12 - epd_7in5_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_7in5_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_7in5_v2_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_7in5_v2_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_7in5_v2_test.o(.text) refers to epd_7in5_v2.o(.text) for EPD_7IN5_V2_Init - epd_7in5_v2_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_7in5_v2_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_7in5_v2_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_7in5_v2_test.o(.text) refers to malloc.o(i.free) for free - epd_7in5_v2_test.o(.text) refers to imagedata.o(.constdata) for gImage_7in5_V2 - epd_7in5_v2_test.o(.text) refers to font16.o(.data) for Font16 - epd_7in5_v2_test.o(.text) refers to font12.o(.data) for Font12 - epd_7in5_v2_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_7in5_v2_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_7in5bc_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_7in5bc_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_7in5bc_test.o(.text) refers to epd_7in5bc.o(.text) for EPD_7IN5BC_Init - epd_7in5bc_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_7in5bc_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_7in5bc_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_7in5bc_test.o(.text) refers to malloc.o(i.free) for free - epd_7in5bc_test.o(.text) refers to imagedata.o(.constdata) for gImage_7in5bc_ry - epd_7in5bc_test.o(.text) refers to imagedata.o(.constdata) for gImage_7in5bc_b - epd_7in5bc_test.o(.text) refers to font16.o(.data) for Font16 - epd_7in5bc_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_7in5bc_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_7in5bc_test.o(.text) refers to font12.o(.data) for Font12 - epd_7in5b_v2_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_7in5b_v2_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_7in5b_v2_test.o(.text) refers to epd_7in5b_v2.o(.text) for EPD_7IN5B_V2_Init - epd_7in5b_v2_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_7in5b_v2_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_7in5b_v2_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_7in5b_v2_test.o(.text) refers to malloc.o(i.free) for free - epd_7in5b_v2_test.o(.text) refers to imagedata.o(.constdata) for gImage_7in5_V2_b - epd_7in5b_v2_test.o(.text) refers to imagedata.o(.constdata) for gImage_7in5_V2_ry - epd_7in5b_v2_test.o(.text) refers to font16.o(.data) for Font16 - epd_7in5b_v2_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_7in5b_v2_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_7in5b_v2_test.o(.text) refers to font12.o(.data) for Font12 - epd_7in5b_hd_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_7in5b_hd_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_7in5b_hd_test.o(.text) refers to epd_7in5b_hd.o(.text) for EPD_7IN5B_HD_Init - epd_7in5b_hd_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_7in5b_hd_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_7in5b_hd_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_7in5b_hd_test.o(.text) refers to malloc.o(i.free) for free - epd_7in5b_hd_test.o(.text) refers to imagedata.o(.constdata) for gImage_7in5_V2_ry - epd_7in5b_hd_test.o(.text) refers to imagedata.o(.constdata) for gImage_7in5_V2_b - epd_7in5b_hd_test.o(.text) refers to font16.o(.data) for Font16 - epd_7in5b_hd_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_7in5b_hd_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_7in5b_hd_test.o(.text) refers to font12.o(.data) for Font12 - epd_7in5_hd_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_7in5_hd_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_7in5_hd_test.o(.text) refers to epd_7in5_hd.o(.text) for EPD_7IN5_HD_Init - epd_7in5_hd_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_7in5_hd_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_7in5_hd_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_7in5_hd_test.o(.text) refers to malloc.o(i.free) for free - epd_7in5_hd_test.o(.text) refers to imagedata.o(.constdata) for gImage_7in5_V2 - epd_7in5_hd_test.o(.text) refers to font16.o(.data) for Font16 - epd_7in5_hd_test.o(.text) refers to font12.o(.data) for Font12 - epd_7in5_hd_test.o(.text) refers to font12cn.o(.data) for Font12CN - epd_7in5_hd_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_1in64g_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_1in64g_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_1in64g_test.o(.text) refers to epd_1in64g.o(.text) for EPD_1IN64G_Init - epd_1in64g_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_1in64g_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_1in64g_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_1in64g_test.o(.text) refers to malloc.o(i.free) for free - epd_1in64g_test.o(.text) refers to imagedata2.o(.constdata) for gImage_1in64g - epd_1in64g_test.o(.text) refers to font16.o(.data) for Font16 - epd_1in64g_test.o(.text) refers to font12.o(.data) for Font12 - epd_1in64g_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_3in0g_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_3in0g_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_3in0g_test.o(.text) refers to epd_3in0g.o(.text) for EPD_3IN0G_Init - epd_3in0g_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_3in0g_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_3in0g_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_3in0g_test.o(.text) refers to malloc.o(i.free) for free - epd_3in0g_test.o(.text) refers to imagedata2.o(.constdata) for gImage_3in0g - epd_3in0g_test.o(.text) refers to font16.o(.data) for Font16 - epd_3in0g_test.o(.text) refers to font12.o(.data) for Font12 - epd_3in0g_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_4in37g_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_4in37g_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_4in37g_test.o(.text) refers to epd_4in37g.o(.text) for EPD_4IN37G_Init - epd_4in37g_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_4in37g_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_4in37g_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_4in37g_test.o(.text) refers to malloc.o(i.free) for free - epd_4in37g_test.o(.text) refers to imagedata2.o(.constdata) for Image4color - epd_4in37g_test.o(.text) refers to font20.o(.data) for Font20 - epd_4in37g_test.o(.text) refers to font12.o(.data) for Font12 - epd_4in37g_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_7in3g_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_7in3g_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_7in3g_test.o(.text) refers to epd_7in3g.o(.text) for EPD_7IN3G_Init - epd_7in3g_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_7in3g_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_7in3g_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_7in3g_test.o(.text) refers to malloc.o(i.free) for free - epd_7in3g_test.o(.text) refers to imagedata2.o(.constdata) for gImage_7in3g - epd_7in3g_test.o(.text) refers to font16.o(.data) for Font16 - epd_7in3g_test.o(.text) refers to font12.o(.data) for Font12 - epd_7in3g_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_2in36g_test.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in36g_test.o(.text) refers to dev_config.o(.text) for DEV_Module_Init - epd_2in36g_test.o(.text) refers to epd_2in36g.o(.text) for EPD_2IN36G_Init - epd_2in36g_test.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in36g_test.o(.text) refers to malloc.o(i.malloc) for malloc - epd_2in36g_test.o(.text) refers to gui_paint.o(.text) for Paint_NewImage - epd_2in36g_test.o(.text) refers to malloc.o(i.free) for free - epd_2in36g_test.o(.text) refers to imagedata2.o(.constdata) for gImage_2in36g - epd_2in36g_test.o(.text) refers to font16.o(.data) for Font16 - epd_2in36g_test.o(.text) refers to font12.o(.data) for Font12 - epd_2in36g_test.o(.text) refers to font24cn.o(.data) for Font24CN - epd_1in02d.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_WritePin - epd_1in02d.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_1in02d.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_1in02d.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_1in02d.o(.text) refers to epd_1in02d.o(.constdata) for .constdata - epd_1in54.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_1in54.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_1in54.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_1in54.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_1in54.o(.text) refers to epd_1in54.o(.constdata) for .constdata - epd_1in54_v2.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_WritePin - epd_1in54_v2.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_1in54_v2.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_1in54_v2.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_1in54_v2.o(.text) refers to epd_1in54_v2.o(.data) for .data - epd_1in54b.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_1in54b.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_1in54b.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_1in54b.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_1in54b.o(.text) refers to epd_1in54b.o(.constdata) for .constdata - epd_1in54b_v2.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_1in54b_v2.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_1in54b_v2.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_1in54b_v2.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_1in54c.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_WritePin - epd_1in54c.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_1in54c.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_2in7.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_WritePin - epd_2in7.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in7.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in7.o(.text) refers to epd_2in7.o(.constdata) for .constdata - epd_2in7.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_2in7b.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in7b.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in7b.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_2in7b.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_2in7b.o(.text) refers to epd_2in7b.o(.constdata) for .constdata - epd_2in7b_v2.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in7b_v2.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in7b_v2.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_2in7b_v2.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_2in9.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in9.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in9.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_2in9.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_2in9.o(.text) refers to epd_2in9.o(.constdata) for .constdata - epd_2in9_v2.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in9_v2.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_2in9_v2.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in9_v2.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_2in9_v2.o(.text) refers to epd_2in9_v2.o(.data) for .data - epd_2in9bc.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in9bc.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in9bc.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_2in9bc.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_2in9b_v3.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in9b_v3.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_2in9b_v3.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in9b_v3.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_2in9d.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in9d.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_2in9d.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in9d.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_2in9d.o(.text) refers to epd_2in9d.o(.constdata) for .constdata - epd_2in13.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in13.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in13.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_2in13.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_2in13.o(.text) refers to epd_2in13.o(.constdata) for .constdata - epd_2in13_v2.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in13_v2.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in13_v2.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_2in13_v2.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_2in13_v2.o(.text) refers to epd_2in13_v2.o(.constdata) for .constdata - epd_2in13_v3.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in13_v3.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_2in13_v3.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in13_v3.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_2in13_v3.o(.text) refers to epd_2in13_v3.o(.data) for .data - epd_2in13bc.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in13bc.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in13bc.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_2in13bc.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_2in13b_v3.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in13b_v3.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_2in13b_v3.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in13b_v3.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_2in13b_v4.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in13b_v4.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_2in13b_v4.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in13b_v4.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_2in13d.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in13d.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_2in13d.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in13d.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_2in13d.o(.text) refers to epd_2in13d.o(.constdata) for .constdata - epd_2in66.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_WritePin - epd_2in66.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in66.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in66.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_2in66.o(.text) refers to epd_2in66.o(.constdata) for .constdata - epd_2in66b.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in66b.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in66b.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_2in66b.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte epd_3in52.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_WritePin epd_3in52.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay epd_3in52.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte epd_3in52.o(.text) refers to printf3.o(i.__0printf$3) for __2printf epd_3in52.o(.text) refers to epd_3in52.o(.constdata) for .constdata epd_3in52.o(.text) refers to epd_3in52.o(.data) for .data - epd_3in7.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_WritePin - epd_3in7.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_3in7.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_3in7.o(.text) refers to epd_3in7.o(.constdata) for .constdata - epd_3in7.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_4in01f.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_WritePin - epd_4in01f.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_4in01f.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_4in2.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_WritePin - epd_4in2.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_4in2.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_4in2.o(.text) refers to epd_4in2.o(.bss) for .bss - epd_4in2.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_4in2.o(.text) refers to epd_4in2.o(.constdata) for .constdata - epd_4in2bc.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_4in2bc.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_4in2bc.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_4in2bc.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_4in2b_v2.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_4in2b_v2.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_4in2b_v2.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_4in2b_v2.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_5in65f.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_WritePin - epd_5in65f.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_5in65f.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_5in83.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_5in83.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_5in83.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_5in83.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_5in83_v2.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_5in83_v2.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_5in83_v2.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_5in83_v2.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_5in83bc.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_5in83bc.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_5in83bc.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_5in83bc.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_5in83b_v2.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_5in83b_v2.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_5in83b_v2.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_5in83b_v2.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_7in5.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_7in5.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_7in5.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_7in5.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_7in5_v2.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_7in5_v2.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_7in5_v2.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_7in5_v2.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_7in5_v2.o(.text) refers to epd_7in5_v2.o(.data) for .data - epd_7in5_hd.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_7in5_hd.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_7in5_hd.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_7in5_hd.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_7in5bc.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_7in5bc.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_7in5bc.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_7in5bc.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_7in5b_v2.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_7in5b_v2.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_7in5b_v2.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_7in5b_v2.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_7in5b_hd.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_7in5b_hd.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_7in5b_hd.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_7in5b_hd.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_1in64g.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_1in64g.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_1in64g.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_1in64g.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_3in0g.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_3in0g.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_3in0g.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_3in0g.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_4in37g.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_4in37g.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_4in37g.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_4in37g.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_7in3g.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_7in3g.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_7in3g.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_7in3g.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte - epd_2in36g.o(.text) refers to printf3.o(i.__0printf$3) for __2printf - epd_2in36g.o(.text) refers to stm32f1xx_hal.o(.text) for HAL_Delay - epd_2in36g.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_ReadPin - epd_2in36g.o(.text) refers to dev_config.o(.text) for DEV_SPI_WriteByte dev_config.o(.text) refers to stm32f1xx_hal_spi.o(.text) for HAL_SPI_Transmit dev_config.o(.text) refers to stm32f1xx_hal_gpio.o(.text) for HAL_GPIO_WritePin dev_config.o(.text) refers to spi.o(.bss) for hspi1 @@ -1164,7 +431,6 @@ Removing Unused input sections from the image. Removing imagedata.o(.constdata), (5630 bytes). Removing imagedata.o(.constdata), (5630 bytes). Removing imagedata.o(.constdata), (5630 bytes). - Removing imagedata.o(.constdata), (10800 bytes). Removing imagedata.o(.constdata), (33606 bytes). Removing imagedata.o(.constdata), (128000 bytes). Removing imagedata.o(.constdata), (15000 bytes). @@ -1184,391 +450,12 @@ Removing Unused input sections from the image. Removing imagedata.o(.constdata), (30720 bytes). Removing imagedata.o(.constdata), (48000 bytes). Removing imagedata.o(.constdata), (48000 bytes). - Removing imagedata2.o(.constdata), (4000 bytes). - Removing imagedata2.o(.constdata), (4000 bytes). - Removing imagedata2.o(.constdata), (7056 bytes). - Removing imagedata2.o(.constdata), (16800 bytes). - Removing imagedata2.o(.constdata), (96000 bytes). - Removing imagedata2.o(.constdata), (47104 bytes). - Removing epd_1in02_test.o(.rev16_text), (4 bytes). - Removing epd_1in02_test.o(.revsh_text), (4 bytes). - Removing epd_1in02_test.o(.rrx_text), (6 bytes). - Removing epd_1in02_test.o(.text), (1124 bytes). - Removing epd_1in54_test.o(.rev16_text), (4 bytes). - Removing epd_1in54_test.o(.revsh_text), (4 bytes). - Removing epd_1in54_test.o(.rrx_text), (6 bytes). - Removing epd_1in54_test.o(.text), (956 bytes). - Removing epd_1in54_v2_test.o(.rev16_text), (4 bytes). - Removing epd_1in54_v2_test.o(.revsh_text), (4 bytes). - Removing epd_1in54_v2_test.o(.rrx_text), (6 bytes). - Removing epd_1in54_v2_test.o(.text), (976 bytes). - Removing epd_1in54b_test.o(.rev16_text), (4 bytes). - Removing epd_1in54b_test.o(.revsh_text), (4 bytes). - Removing epd_1in54b_test.o(.rrx_text), (6 bytes). - Removing epd_1in54b_test.o(.text), (948 bytes). - Removing epd_1in54b_v2_test.o(.rev16_text), (4 bytes). - Removing epd_1in54b_v2_test.o(.revsh_text), (4 bytes). - Removing epd_1in54b_v2_test.o(.rrx_text), (6 bytes). - Removing epd_1in54b_v2_test.o(.text), (916 bytes). - Removing epd_1in54c_test.o(.rev16_text), (4 bytes). - Removing epd_1in54c_test.o(.revsh_text), (4 bytes). - Removing epd_1in54c_test.o(.rrx_text), (6 bytes). - Removing epd_1in54c_test.o(.text), (888 bytes). - Removing epd_2in7_test.o(.rev16_text), (4 bytes). - Removing epd_2in7_test.o(.revsh_text), (4 bytes). - Removing epd_2in7_test.o(.rrx_text), (6 bytes). - Removing epd_2in7_test.o(.text), (1352 bytes). - Removing epd_2in7b_test.o(.rev16_text), (4 bytes). - Removing epd_2in7b_test.o(.revsh_text), (4 bytes). - Removing epd_2in7b_test.o(.rrx_text), (6 bytes). - Removing epd_2in7b_test.o(.text), (944 bytes). - Removing epd_2in7b_v2_test.o(.rev16_text), (4 bytes). - Removing epd_2in7b_v2_test.o(.revsh_text), (4 bytes). - Removing epd_2in7b_v2_test.o(.rrx_text), (6 bytes). - Removing epd_2in7b_v2_test.o(.text), (960 bytes). - Removing epd_2in9_test.o(.rev16_text), (4 bytes). - Removing epd_2in9_test.o(.revsh_text), (4 bytes). - Removing epd_2in9_test.o(.rrx_text), (6 bytes). - Removing epd_2in9_test.o(.text), (1028 bytes). - Removing epd_2in9_v2_test.o(.rev16_text), (4 bytes). - Removing epd_2in9_v2_test.o(.revsh_text), (4 bytes). - Removing epd_2in9_v2_test.o(.rrx_text), (6 bytes). - Removing epd_2in9_v2_test.o(.text), (1080 bytes). - Removing epd_2in9bc_test.o(.rev16_text), (4 bytes). - Removing epd_2in9bc_test.o(.revsh_text), (4 bytes). - Removing epd_2in9bc_test.o(.rrx_text), (6 bytes). - Removing epd_2in9bc_test.o(.text), (928 bytes). - Removing epd_2in9b_v3_test.o(.rev16_text), (4 bytes). - Removing epd_2in9b_v3_test.o(.revsh_text), (4 bytes). - Removing epd_2in9b_v3_test.o(.rrx_text), (6 bytes). - Removing epd_2in9b_v3_test.o(.text), (932 bytes). - Removing epd_2in9d_test.o(.rev16_text), (4 bytes). - Removing epd_2in9d_test.o(.revsh_text), (4 bytes). - Removing epd_2in9d_test.o(.rrx_text), (6 bytes). - Removing epd_2in9d_test.o(.text), (1068 bytes). - Removing epd_2in13_test.o(.rev16_text), (4 bytes). - Removing epd_2in13_test.o(.revsh_text), (4 bytes). - Removing epd_2in13_test.o(.rrx_text), (6 bytes). - Removing epd_2in13_test.o(.text), (960 bytes). - Removing epd_2in13_v2_test.o(.rev16_text), (4 bytes). - Removing epd_2in13_v2_test.o(.revsh_text), (4 bytes). - Removing epd_2in13_v2_test.o(.rrx_text), (6 bytes). - Removing epd_2in13_v2_test.o(.text), (1012 bytes). - Removing epd_2in13_v3_test.o(.rev16_text), (4 bytes). - Removing epd_2in13_v3_test.o(.revsh_text), (4 bytes). - Removing epd_2in13_v3_test.o(.rrx_text), (6 bytes). - Removing epd_2in13_v3_test.o(.text), (1064 bytes). - Removing epd_2in13b_v3_test.o(.rev16_text), (4 bytes). - Removing epd_2in13b_v3_test.o(.revsh_text), (4 bytes). - Removing epd_2in13b_v3_test.o(.rrx_text), (6 bytes). - Removing epd_2in13b_v3_test.o(.text), (912 bytes). - Removing epd_2in13b_v4_test.o(.rev16_text), (4 bytes). - Removing epd_2in13b_v4_test.o(.revsh_text), (4 bytes). - Removing epd_2in13b_v4_test.o(.rrx_text), (6 bytes). - Removing epd_2in13b_v4_test.o(.text), (920 bytes). - Removing epd_2in13bc_test.o(.rev16_text), (4 bytes). - Removing epd_2in13bc_test.o(.revsh_text), (4 bytes). - Removing epd_2in13bc_test.o(.rrx_text), (6 bytes). - Removing epd_2in13bc_test.o(.text), (908 bytes). - Removing epd_2in13d_test.o(.rev16_text), (4 bytes). - Removing epd_2in13d_test.o(.revsh_text), (4 bytes). - Removing epd_2in13d_test.o(.rrx_text), (6 bytes). - Removing epd_2in13d_test.o(.text), (964 bytes). - Removing epd_2in66_test.o(.rev16_text), (4 bytes). - Removing epd_2in66_test.o(.revsh_text), (4 bytes). - Removing epd_2in66_test.o(.rrx_text), (6 bytes). - Removing epd_2in66_test.o(.text), (1072 bytes). - Removing epd_2in66b_test.o(.rev16_text), (4 bytes). - Removing epd_2in66b_test.o(.revsh_text), (4 bytes). - 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Removing epd_3in52_test.o(.rrx_text), (6 bytes). - Removing epd_3in52_test.o(.text), (820 bytes). - Removing epd_3in7_test.o(.rev16_text), (4 bytes). - Removing epd_3in7_test.o(.revsh_text), (4 bytes). - Removing epd_3in7_test.o(.rrx_text), (6 bytes). - Removing epd_3in7_test.o(.text), (1280 bytes). - Removing epd_4in01f_test.o(.rev16_text), (4 bytes). - Removing epd_4in01f_test.o(.revsh_text), (4 bytes). - Removing epd_4in01f_test.o(.rrx_text), (6 bytes). - Removing epd_4in01f_test.o(.text), (968 bytes). - Removing epd_4in2_test.o(.rev16_text), (4 bytes). - Removing epd_4in2_test.o(.revsh_text), (4 bytes). - Removing epd_4in2_test.o(.rrx_text), (6 bytes). - Removing epd_4in2_test.o(.text), (1404 bytes). - Removing epd_4in2_test.o(.conststring), (93 bytes). - Removing epd_4in2bc_test.o(.rev16_text), (4 bytes). - Removing epd_4in2bc_test.o(.revsh_text), (4 bytes). - Removing epd_4in2bc_test.o(.rrx_text), (6 bytes). - Removing epd_4in2bc_test.o(.text), (984 bytes). - Removing epd_4in2b_v2_test.o(.rev16_text), (4 bytes). - Removing epd_4in2b_v2_test.o(.revsh_text), (4 bytes). - Removing epd_4in2b_v2_test.o(.rrx_text), (6 bytes). - Removing epd_4in2b_v2_test.o(.text), (992 bytes). - Removing epd_5in65f_test.o(.rev16_text), (4 bytes). - Removing epd_5in65f_test.o(.revsh_text), (4 bytes). - Removing epd_5in65f_test.o(.rrx_text), (6 bytes). - Removing epd_5in65f_test.o(.text), (948 bytes). - Removing epd_5in83_test.o(.rev16_text), (4 bytes). - Removing epd_5in83_test.o(.revsh_text), (4 bytes). - Removing epd_5in83_test.o(.rrx_text), (6 bytes). - Removing epd_5in83_test.o(.text), (852 bytes). - Removing epd_5in83_v2_test.o(.rev16_text), (4 bytes). - Removing epd_5in83_v2_test.o(.revsh_text), (4 bytes). - Removing epd_5in83_v2_test.o(.rrx_text), (6 bytes). - Removing epd_5in83_v2_test.o(.text), (872 bytes). - Removing epd_5in83bc_test.o(.rev16_text), (4 bytes). - Removing epd_5in83bc_test.o(.revsh_text), (4 bytes). - Removing epd_5in83bc_test.o(.rrx_text), (6 bytes). - Removing epd_5in83bc_test.o(.text), (924 bytes). - Removing epd_5in83b_v2_test.o(.rev16_text), (4 bytes). - Removing epd_5in83b_v2_test.o(.revsh_text), (4 bytes). - Removing epd_5in83b_v2_test.o(.rrx_text), (6 bytes). - Removing epd_5in83b_v2_test.o(.text), (1204 bytes). - Removing epd_7in5_test.o(.rev16_text), (4 bytes). - Removing epd_7in5_test.o(.revsh_text), (4 bytes). - Removing epd_7in5_test.o(.rrx_text), (6 bytes). - Removing epd_7in5_test.o(.text), (852 bytes). - Removing epd_7in5_v2_test.o(.rev16_text), (4 bytes). - Removing epd_7in5_v2_test.o(.revsh_text), (4 bytes). - Removing epd_7in5_v2_test.o(.rrx_text), (6 bytes). - Removing epd_7in5_v2_test.o(.text), (896 bytes). - Removing epd_7in5bc_test.o(.rev16_text), (4 bytes). - Removing epd_7in5bc_test.o(.revsh_text), (4 bytes). - Removing epd_7in5bc_test.o(.rrx_text), (6 bytes). - Removing epd_7in5bc_test.o(.text), (924 bytes). - Removing epd_7in5b_v2_test.o(.rev16_text), (4 bytes). - Removing epd_7in5b_v2_test.o(.revsh_text), (4 bytes). - Removing epd_7in5b_v2_test.o(.rrx_text), (6 bytes). - Removing epd_7in5b_v2_test.o(.text), (884 bytes). - Removing epd_7in5b_hd_test.o(.rev16_text), (4 bytes). - Removing epd_7in5b_hd_test.o(.revsh_text), (4 bytes). - Removing epd_7in5b_hd_test.o(.rrx_text), (6 bytes). - Removing epd_7in5b_hd_test.o(.text), (872 bytes). - Removing epd_7in5_hd_test.o(.rev16_text), (4 bytes). - Removing epd_7in5_hd_test.o(.revsh_text), (4 bytes). - Removing epd_7in5_hd_test.o(.rrx_text), (6 bytes). - Removing epd_7in5_hd_test.o(.text), (888 bytes). - Removing epd_1in64g_test.o(.rev16_text), (4 bytes). - Removing epd_1in64g_test.o(.revsh_text), (4 bytes). - Removing epd_1in64g_test.o(.rrx_text), (6 bytes). - Removing epd_1in64g_test.o(.text), (1136 bytes). - Removing epd_3in0g_test.o(.rev16_text), (4 bytes). - Removing epd_3in0g_test.o(.revsh_text), (4 bytes). - Removing epd_3in0g_test.o(.rrx_text), (6 bytes). - Removing epd_3in0g_test.o(.text), (1168 bytes). - Removing epd_4in37g_test.o(.rev16_text), (4 bytes). - Removing epd_4in37g_test.o(.revsh_text), (4 bytes). - Removing epd_4in37g_test.o(.rrx_text), (6 bytes). - Removing epd_4in37g_test.o(.text), (1052 bytes). - Removing epd_7in3g_test.o(.rev16_text), (4 bytes). - Removing epd_7in3g_test.o(.revsh_text), (4 bytes). - Removing epd_7in3g_test.o(.rrx_text), (6 bytes). - Removing epd_7in3g_test.o(.text), (924 bytes). - Removing epd_2in36g_test.o(.rev16_text), (4 bytes). - Removing epd_2in36g_test.o(.revsh_text), (4 bytes). - Removing epd_2in36g_test.o(.rrx_text), (6 bytes). - Removing epd_1in02d.o(.rev16_text), (4 bytes). - Removing epd_1in02d.o(.revsh_text), (4 bytes). - Removing epd_1in02d.o(.rrx_text), (6 bytes). - Removing epd_1in02d.o(.text), (1036 bytes). - Removing epd_1in02d.o(.constdata), (168 bytes). - Removing epd_1in54.o(.rev16_text), (4 bytes). - Removing epd_1in54.o(.revsh_text), (4 bytes). - Removing epd_1in54.o(.rrx_text), (6 bytes). - Removing epd_1in54.o(.text), (776 bytes). - Removing epd_1in54.o(.constdata), (60 bytes). - Removing epd_1in54_v2.o(.rev16_text), (4 bytes). - Removing epd_1in54_v2.o(.revsh_text), (4 bytes). - Removing epd_1in54_v2.o(.rrx_text), (6 bytes). - Removing epd_1in54_v2.o(.text), (1024 bytes). - Removing epd_1in54_v2.o(.data), (318 bytes). - Removing epd_1in54b.o(.rev16_text), (4 bytes). - Removing epd_1in54b.o(.revsh_text), (4 bytes). - Removing epd_1in54b.o(.rrx_text), (6 bytes). - Removing epd_1in54b.o(.text), (996 bytes). - Removing epd_1in54b.o(.constdata), (120 bytes). - Removing epd_1in54b_v2.o(.rev16_text), (4 bytes). - Removing epd_1in54b_v2.o(.revsh_text), (4 bytes). - Removing epd_1in54b_v2.o(.rrx_text), (6 bytes). - Removing epd_1in54b_v2.o(.text), (584 bytes). - Removing epd_1in54c.o(.rev16_text), (4 bytes). - Removing epd_1in54c.o(.revsh_text), (4 bytes). - Removing epd_1in54c.o(.rrx_text), (6 bytes). - Removing epd_1in54c.o(.text), (500 bytes). - Removing epd_2in7.o(.rev16_text), (4 bytes). - Removing epd_2in7.o(.revsh_text), (4 bytes). - Removing epd_2in7.o(.rrx_text), (6 bytes). - Removing epd_2in7.o(.text), (1540 bytes). - Removing epd_2in7.o(.constdata), (424 bytes). - Removing epd_2in7b.o(.rev16_text), (4 bytes). - Removing epd_2in7b.o(.revsh_text), (4 bytes). - Removing epd_2in7b.o(.rrx_text), (6 bytes). - Removing epd_2in7b.o(.text), (864 bytes). - Removing epd_2in7b.o(.constdata), (212 bytes). - Removing epd_2in7b_v2.o(.rev16_text), (4 bytes). - Removing epd_2in7b_v2.o(.revsh_text), (4 bytes). - Removing epd_2in7b_v2.o(.rrx_text), (6 bytes). - Removing epd_2in7b_v2.o(.text), (600 bytes). - Removing epd_2in9.o(.rev16_text), (4 bytes). - Removing epd_2in9.o(.revsh_text), (4 bytes). - Removing epd_2in9.o(.rrx_text), (6 bytes). - Removing epd_2in9.o(.text), (792 bytes). - Removing epd_2in9.o(.constdata), (60 bytes). - Removing epd_2in9_v2.o(.rev16_text), (4 bytes). - Removing epd_2in9_v2.o(.revsh_text), (4 bytes). - Removing epd_2in9_v2.o(.rrx_text), (6 bytes). - Removing epd_2in9_v2.o(.text), (968 bytes). - Removing epd_2in9_v2.o(.data), (318 bytes). - Removing epd_2in9bc.o(.rev16_text), (4 bytes). - Removing epd_2in9bc.o(.revsh_text), (4 bytes). - Removing epd_2in9bc.o(.rrx_text), (6 bytes). - Removing epd_2in9bc.o(.text), (576 bytes). - Removing epd_2in9b_v3.o(.rev16_text), (4 bytes). - Removing epd_2in9b_v3.o(.revsh_text), (4 bytes). - Removing epd_2in9b_v3.o(.rrx_text), (6 bytes). - Removing epd_2in9b_v3.o(.text), (556 bytes). - Removing epd_2in9d.o(.rev16_text), (4 bytes). - Removing epd_2in9d.o(.revsh_text), (4 bytes). - Removing epd_2in9d.o(.rrx_text), (6 bytes). - Removing epd_2in9d.o(.text), (1012 bytes). - Removing epd_2in9d.o(.constdata), (212 bytes). - Removing epd_2in13.o(.rev16_text), (4 bytes). - Removing epd_2in13.o(.revsh_text), (4 bytes). - Removing epd_2in13.o(.rrx_text), (6 bytes). - Removing epd_2in13.o(.text), (796 bytes). - Removing epd_2in13.o(.constdata), (60 bytes). - Removing epd_2in13_v2.o(.rev16_text), (4 bytes). - Removing epd_2in13_v2.o(.revsh_text), (4 bytes). - Removing epd_2in13_v2.o(.rrx_text), (6 bytes). - Removing epd_2in13_v2.o(.text), (1072 bytes). - Removing epd_2in13_v2.o(.constdata), (152 bytes). - Removing epd_2in13_v3.o(.rev16_text), (4 bytes). - Removing epd_2in13_v3.o(.revsh_text), (4 bytes). - Removing epd_2in13_v3.o(.rrx_text), (6 bytes). - Removing epd_2in13_v3.o(.text), (1078 bytes). - Removing epd_2in13_v3.o(.data), (318 bytes). - Removing epd_2in13bc.o(.rev16_text), (4 bytes). - Removing epd_2in13bc.o(.revsh_text), (4 bytes). - Removing epd_2in13bc.o(.rrx_text), (6 bytes). - Removing epd_2in13bc.o(.text), (588 bytes). - Removing epd_2in13b_v3.o(.rev16_text), (4 bytes). - Removing epd_2in13b_v3.o(.revsh_text), (4 bytes). - Removing epd_2in13b_v3.o(.rrx_text), (6 bytes). - Removing epd_2in13b_v3.o(.text), (580 bytes). - Removing epd_2in13b_v4.o(.rev16_text), (4 bytes). - Removing epd_2in13b_v4.o(.revsh_text), (4 bytes). - Removing epd_2in13b_v4.o(.rrx_text), (6 bytes). - Removing epd_2in13b_v4.o(.text), (648 bytes). - Removing epd_2in13d.o(.rev16_text), (4 bytes). - Removing epd_2in13d.o(.revsh_text), (4 bytes). - Removing epd_2in13d.o(.rrx_text), (6 bytes). - Removing epd_2in13d.o(.text), (1076 bytes). - Removing epd_2in13d.o(.constdata), (424 bytes). - Removing epd_2in66.o(.rev16_text), (4 bytes). - Removing epd_2in66.o(.revsh_text), (4 bytes). - Removing epd_2in66.o(.rrx_text), (6 bytes). - Removing epd_2in66.o(.text), (704 bytes). - Removing epd_2in66.o(.constdata), (159 bytes). - Removing epd_2in66b.o(.rev16_text), (4 bytes). - Removing epd_2in66b.o(.revsh_text), (4 bytes). - Removing epd_2in66b.o(.rrx_text), (6 bytes). - Removing epd_2in66b.o(.text), (608 bytes). Removing epd_3in52.o(.rev16_text), (4 bytes). Removing epd_3in52.o(.revsh_text), (4 bytes). Removing epd_3in52.o(.rrx_text), (6 bytes). - Removing epd_3in52.o(.text), (1228 bytes). - Removing epd_3in52.o(.constdata), (714 bytes). - Removing epd_3in52.o(.data), (1 bytes). - Removing epd_3in7.o(.rev16_text), (4 bytes). - Removing epd_3in7.o(.revsh_text), (4 bytes). - Removing epd_3in7.o(.rrx_text), (6 bytes). - Removing epd_3in7.o(.text), (1928 bytes). - Removing epd_3in7.o(.constdata), (420 bytes). - Removing epd_4in01f.o(.rev16_text), (4 bytes). - Removing epd_4in01f.o(.revsh_text), (4 bytes). - Removing epd_4in01f.o(.rrx_text), (6 bytes). - Removing epd_4in01f.o(.text), (792 bytes). - Removing epd_4in2.o(.rev16_text), (4 bytes). - Removing epd_4in2.o(.revsh_text), (4 bytes). - Removing epd_4in2.o(.rrx_text), (6 bytes). - Removing epd_4in2.o(.text), (2016 bytes). - Removing epd_4in2.o(.bss), (15000 bytes). - Removing epd_4in2.o(.constdata), (668 bytes). - Removing epd_4in2bc.o(.rev16_text), (4 bytes). - Removing epd_4in2bc.o(.revsh_text), (4 bytes). - Removing epd_4in2bc.o(.rrx_text), (6 bytes). - Removing epd_4in2bc.o(.text), (528 bytes). - Removing epd_4in2b_v2.o(.rev16_text), (4 bytes). - Removing epd_4in2b_v2.o(.revsh_text), (4 bytes). - Removing epd_4in2b_v2.o(.rrx_text), (6 bytes). - Removing epd_4in2b_v2.o(.text), (524 bytes). - Removing epd_5in65f.o(.rev16_text), (4 bytes). - Removing epd_5in65f.o(.revsh_text), (4 bytes). - Removing epd_5in65f.o(.rrx_text), (6 bytes). - Removing epd_5in65f.o(.text), (840 bytes). - Removing epd_5in83.o(.rev16_text), (4 bytes). - Removing epd_5in83.o(.revsh_text), (4 bytes). - Removing epd_5in83.o(.rrx_text), (6 bytes). - Removing epd_5in83.o(.text), (640 bytes). - Removing epd_5in83_v2.o(.rev16_text), (4 bytes). - Removing epd_5in83_v2.o(.revsh_text), (4 bytes). - Removing epd_5in83_v2.o(.rrx_text), (6 bytes). - Removing epd_5in83_v2.o(.text), (600 bytes). - Removing epd_5in83bc.o(.rev16_text), (4 bytes). - Removing epd_5in83bc.o(.revsh_text), (4 bytes). - Removing epd_5in83bc.o(.rrx_text), (6 bytes). - Removing epd_5in83bc.o(.text), (844 bytes). - Removing epd_5in83b_v2.o(.rev16_text), (4 bytes). - Removing epd_5in83b_v2.o(.revsh_text), (4 bytes). - Removing epd_5in83b_v2.o(.rrx_text), (6 bytes). - Removing epd_5in83b_v2.o(.text), (1180 bytes). - Removing epd_7in5.o(.rev16_text), (4 bytes). - Removing epd_7in5.o(.revsh_text), (4 bytes). - Removing epd_7in5.o(.rrx_text), (6 bytes). - Removing epd_7in5.o(.text), (640 bytes). - Removing epd_7in5_v2.o(.rev16_text), (4 bytes). - Removing epd_7in5_v2.o(.revsh_text), (4 bytes). - Removing epd_7in5_v2.o(.rrx_text), (6 bytes). - Removing epd_7in5_v2.o(.text), (940 bytes). - Removing epd_7in5_v2.o(.data), (217 bytes). - Removing epd_7in5_hd.o(.rev16_text), (4 bytes). - Removing epd_7in5_hd.o(.revsh_text), (4 bytes). - Removing epd_7in5_hd.o(.rrx_text), (6 bytes). - Removing epd_7in5_hd.o(.text), (1060 bytes). - Removing epd_7in5bc.o(.rev16_text), (4 bytes). - Removing epd_7in5bc.o(.revsh_text), (4 bytes). - Removing epd_7in5bc.o(.rrx_text), (6 bytes). - Removing epd_7in5bc.o(.text), (860 bytes). - Removing epd_7in5b_v2.o(.rev16_text), (4 bytes). - Removing epd_7in5b_v2.o(.revsh_text), (4 bytes). - Removing epd_7in5b_v2.o(.rrx_text), (6 bytes). - Removing epd_7in5b_v2.o(.text), (880 bytes). - Removing epd_7in5b_hd.o(.rev16_text), (4 bytes). - Removing epd_7in5b_hd.o(.revsh_text), (4 bytes). - Removing epd_7in5b_hd.o(.rrx_text), (6 bytes). - Removing epd_7in5b_hd.o(.text), (1352 bytes). - Removing epd_1in64g.o(.rev16_text), (4 bytes). - Removing epd_1in64g.o(.revsh_text), (4 bytes). - Removing epd_1in64g.o(.rrx_text), (6 bytes). - Removing epd_1in64g.o(.text), (736 bytes). - Removing epd_3in0g.o(.rev16_text), (4 bytes). - Removing epd_3in0g.o(.revsh_text), (4 bytes). - Removing epd_3in0g.o(.rrx_text), (6 bytes). - Removing epd_3in0g.o(.text), (656 bytes). - Removing epd_4in37g.o(.rev16_text), (4 bytes). - Removing epd_4in37g.o(.revsh_text), (4 bytes). - Removing epd_4in37g.o(.rrx_text), (6 bytes). - Removing epd_4in37g.o(.text), (748 bytes). - Removing epd_7in3g.o(.rev16_text), (4 bytes). - Removing epd_7in3g.o(.revsh_text), (4 bytes). - Removing epd_7in3g.o(.rrx_text), (6 bytes). - Removing epd_7in3g.o(.text), (884 bytes). - Removing epd_2in36g.o(.rev16_text), (4 bytes). - Removing epd_2in36g.o(.revsh_text), (4 bytes). - Removing epd_2in36g.o(.rrx_text), (6 bytes). Removing dev_config.o(.rev16_text), (4 bytes). Removing dev_config.o(.revsh_text), (4 bytes). Removing dev_config.o(.rrx_text), (6 bytes). @@ -1583,6 +470,8 @@ Removing Unused input sections from the image. Removing font20.o(.data), (8 bytes). Removing font24.o(.constdata), (6840 bytes). Removing font24.o(.data), (8 bytes). + Removing font24cn.o(.constdata), (4482 bytes). + Removing font24cn.o(.data), (12 bytes). Removing system_stm32f1xx.o(.rev16_text), (4 bytes). Removing system_stm32f1xx.o(.revsh_text), (4 bytes). Removing system_stm32f1xx.o(.rrx_text), (6 bytes). @@ -1645,7 +534,7 @@ Removing Unused input sections from the image. Removing cdrcmple.o(.text), (48 bytes). Removing depilogue.o(.text), (186 bytes). -523 unused section(s) (total 1125310 bytes) removed from the image. +145 unused section(s) (total 840144 bytes) removed from the image. ============================================================================== @@ -1677,40 +566,40 @@ Image Symbol Table ../Src/stm32f1xx_it.c 0x00000000 Number 0 stm32f1xx_it.o ABSOLUTE ../Src/system_stm32f1xx.c 0x00000000 Number 0 system_stm32f1xx.o ABSOLUTE ../Src/usart.c 0x00000000 Number 0 usart.o ABSOLUTE - ../clib/microlib/division.c 0x00000000 Number 0 uldiv.o ABSOLUTE ../clib/microlib/division.c 0x00000000 Number 0 uidiv.o ABSOLUTE + ../clib/microlib/division.c 0x00000000 Number 0 uldiv.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11a.o ABSOLUTE ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9b.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8a.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9a.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry5.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry.o ABSOLUTE ../clib/microlib/init/entry.s 0x00000000 Number 0 entry2.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10b.o ABSOLUTE ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7a.o ABSOLUTE ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7b.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11a.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11b.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10b.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8a.o ABSOLUTE ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8b.o ABSOLUTE - ../clib/microlib/longlong.c 0x00000000 Number 0 llsshr.o ABSOLUTE + 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ABSOLUTE - ..\\User\\e-Paper\\EPD_7in5b_V2.c 0x00000000 Number 0 epd_7in5b_v2.o ABSOLUTE - ..\\User\\e-Paper\\EPD_7in5bc.c 0x00000000 Number 0 epd_7in5bc.o ABSOLUTE cdrcmple.s 0x00000000 Number 0 cdrcmple.o ABSOLUTE dc.s 0x00000000 Number 0 dc.o ABSOLUTE handlers.s 0x00000000 Number 0 handlers.o ABSOLUTE @@ -1960,98 +672,109 @@ Image Symbol Table .text 0x0800031c Section 0 usart.o(.text) .text 0x080003f4 Section 0 stm32f1xx_it.o(.text) .text 0x08000424 Section 0 stm32f1xx_hal_msp.o(.text) - .text 0x08000460 Section 0 epd_2in36g_test.o(.text) - .text 0x080009b0 Section 0 epd_2in36g.o(.text) - EPD_2IN36G_ReadBusyH 0x080009b1 Thumb Code 40 epd_2in36g.o(.text) - EPD_2IN36G_SendCommand 0x08000bc9 Thumb Code 46 epd_2in36g.o(.text) - EPD_2IN36G_SendData 0x08000bf7 Thumb Code 46 epd_2in36g.o(.text) - EPD_2IN36G_TurnOnDisplay 0x08000c25 Thumb Code 36 epd_2in36g.o(.text) - .text 0x08000c84 Section 0 dev_config.o(.text) - .text 0x08000cec Section 0 gui_paint.o(.text) - .text 0x08001b98 Section 0 system_stm32f1xx.o(.text) - .text 0x08001c5c Section 0 stm32f1xx_hal_spi.o(.text) - SPI_WaitFlagStateUntilTimeout 0x08001d45 Thumb Code 210 stm32f1xx_hal_spi.o(.text) - SPI_EndRxTxTransaction 0x08001e17 Thumb Code 36 stm32f1xx_hal_spi.o(.text) - SPI_EndRxTransaction 0x08001fd7 Thumb Code 112 stm32f1xx_hal_spi.o(.text) - SPI_CloseTx_ISR 0x080023b7 Thumb Code 130 stm32f1xx_hal_spi.o(.text) - SPI_TxISR_8BIT 0x08002439 Thumb Code 30 stm32f1xx_hal_spi.o(.text) - SPI_TxISR_16BIT 0x08002457 Thumb Code 30 stm32f1xx_hal_spi.o(.text) - SPI_CloseRx_ISR 0x08002519 Thumb Code 76 stm32f1xx_hal_spi.o(.text) - SPI_RxISR_8BIT 0x08002565 Thumb Code 30 stm32f1xx_hal_spi.o(.text) - SPI_RxISR_16BIT 0x08002583 Thumb Code 30 stm32f1xx_hal_spi.o(.text) - SPI_CloseRxTx_ISR 0x080025a3 Thumb Code 158 stm32f1xx_hal_spi.o(.text) - SPI_2linesTxISR_8BIT 0x08002641 Thumb Code 46 stm32f1xx_hal_spi.o(.text) - SPI_2linesRxISR_8BIT 0x0800266f Thumb Code 46 stm32f1xx_hal_spi.o(.text) - SPI_2linesTxISR_16BIT 0x0800269d Thumb Code 46 stm32f1xx_hal_spi.o(.text) - SPI_2linesRxISR_16BIT 0x080026cb Thumb Code 46 stm32f1xx_hal_spi.o(.text) - SPI_DMAError 0x08002865 Thumb Code 34 stm32f1xx_hal_spi.o(.text) - SPI_DMATransmitCplt 0x08002887 Thumb Code 102 stm32f1xx_hal_spi.o(.text) - SPI_DMAHalfTransmitCplt 0x080028ef Thumb Code 10 stm32f1xx_hal_spi.o(.text) - SPI_DMAReceiveCplt 0x080029c9 Thumb Code 110 stm32f1xx_hal_spi.o(.text) - SPI_DMAHalfReceiveCplt 0x08002a39 Thumb Code 10 stm32f1xx_hal_spi.o(.text) - SPI_DMATransmitReceiveCplt 0x08002a43 Thumb Code 92 stm32f1xx_hal_spi.o(.text) - SPI_DMAHalfTransmitReceiveCplt 0x08002aa1 Thumb Code 10 stm32f1xx_hal_spi.o(.text) - SPI_AbortRx_ISR 0x08002cef Thumb Code 82 stm32f1xx_hal_spi.o(.text) - SPI_AbortTx_ISR 0x08002d41 Thumb Code 28 stm32f1xx_hal_spi.o(.text) - SPI_DMARxAbortCallback 0x08002e81 Thumb Code 98 stm32f1xx_hal_spi.o(.text) - SPI_DMATxAbortCallback 0x08002ee3 Thumb Code 114 stm32f1xx_hal_spi.o(.text) - SPI_DMAAbortOnError 0x0800312d Thumb Code 16 stm32f1xx_hal_spi.o(.text) - .text 0x08003244 Section 0 stm32f1xx_hal.o(.text) - .text 0x080033cc Section 0 stm32f1xx_hal_rcc.o(.text) - RCC_Delay 0x080034c7 Thumb Code 32 stm32f1xx_hal_rcc.o(.text) - .text 0x08003c94 Section 0 stm32f1xx_hal_gpio.o(.text) - .text 0x08004068 Section 0 stm32f1xx_hal_dma.o(.text) - DMA_SetConfig 0x08004177 Thumb Code 56 stm32f1xx_hal_dma.o(.text) - .text 0x08004cb0 Section 0 stm32f1xx_hal_cortex.o(.text) - .text 0x08004ed4 Section 0 stm32f1xx_hal_uart.o(.text) - UART_SetConfig 0x08004ed5 Thumb Code 194 stm32f1xx_hal_uart.o(.text) - UART_WaitOnFlagUntilTimeout 0x080051b5 Thumb Code 120 stm32f1xx_hal_uart.o(.text) - UART_EndRxTransfer 0x08005465 Thumb Code 28 stm32f1xx_hal_uart.o(.text) - UART_EndTxTransfer 0x08005481 Thumb Code 18 stm32f1xx_hal_uart.o(.text) - UART_DMAError 0x08005493 Thumb Code 74 stm32f1xx_hal_uart.o(.text) - UART_DMATxHalfCplt 0x080054df Thumb Code 10 stm32f1xx_hal_uart.o(.text) - UART_DMATransmitCplt 0x080054eb Thumb Code 48 stm32f1xx_hal_uart.o(.text) - UART_DMARxHalfCplt 0x080055a7 Thumb Code 10 stm32f1xx_hal_uart.o(.text) - UART_DMAReceiveCplt 0x080055b3 Thumb Code 62 stm32f1xx_hal_uart.o(.text) - UART_DMARxAbortCallback 0x080058e7 Thumb Code 44 stm32f1xx_hal_uart.o(.text) - UART_DMATxAbortCallback 0x08005913 Thumb Code 66 stm32f1xx_hal_uart.o(.text) - UART_DMATxOnlyAbortCallback 0x08005a09 Thumb Code 20 stm32f1xx_hal_uart.o(.text) - UART_DMARxOnlyAbortCallback 0x08005a7d Thumb Code 20 stm32f1xx_hal_uart.o(.text) - UART_EndTransmit_IT 0x08005af9 Thumb Code 26 stm32f1xx_hal_uart.o(.text) - UART_Transmit_IT 0x08005b13 Thumb Code 94 stm32f1xx_hal_uart.o(.text) - UART_DMAAbortOnError 0x08005b71 Thumb Code 16 stm32f1xx_hal_uart.o(.text) - UART_Receive_IT 0x08005b81 Thumb Code 146 stm32f1xx_hal_uart.o(.text) - .text 0x08005e70 Section 0 memseta.o(.text) - .text 0x08005e94 Section 0 uidiv.o(.text) - .text 0x08005ec0 Section 36 init.o(.text) - i.__0printf$3 0x08005ee4 Section 0 printf3.o(i.__0printf$3) - i.__scatterload_copy 0x08005f04 Section 14 handlers.o(i.__scatterload_copy) - i.__scatterload_null 0x08005f12 Section 2 handlers.o(i.__scatterload_null) - i.__scatterload_zeroinit 0x08005f14 Section 14 handlers.o(i.__scatterload_zeroinit) - i._printf_core 0x08005f24 Section 0 printf3.o(i._printf_core) - _printf_core 0x08005f25 Thumb Code 436 printf3.o(i._printf_core) - i.free 0x080060dc Section 0 malloc.o(i.free) - i.malloc 0x0800612c Section 0 malloc.o(i.malloc) - .constdata 0x08006198 Section 12432 imagedata2.o(.constdata) - .constdata 0x08009228 Section 1140 font12.o(.constdata) - .constdata 0x0800969c Section 3040 font16.o(.constdata) - .constdata 0x0800a27c Section 4482 font24cn.o(.constdata) - .constdata 0x0800b3fe Section 16 system_stm32f1xx.o(.constdata) - .constdata 0x0800b40e Section 8 system_stm32f1xx.o(.constdata) - .conststring 0x0800b418 Section 233 gui_paint.o(.conststring) - .data 0x20000000 Section 8 font12.o(.data) - .data 0x20000008 Section 8 font16.o(.data) - .data 0x20000010 Section 12 font24cn.o(.data) - .data 0x2000001c Section 4 system_stm32f1xx.o(.data) - .data 0x20000020 Section 12 stm32f1xx_hal.o(.data) - .data 0x2000002c Section 4 stdout.o(.data) - .data 0x20000030 Section 4 mvars.o(.data) - .data 0x20000034 Section 4 mvars.o(.data) - .bss 0x20000038 Section 88 spi.o(.bss) - .bss 0x20000090 Section 64 usart.o(.bss) - .bss 0x200000d0 Section 24 gui_paint.o(.bss) - HEAP 0x200000e8 Section 49152 startup_stm32f103xe.o(HEAP) - STACK 0x2000c0e8 Section 4096 startup_stm32f103xe.o(STACK) + .text 0x08000460 Section 0 epd_3in52_test.o(.text) + .text 0x08000794 Section 0 epd_3in52.o(.text) + .text 0x08000c60 Section 0 dev_config.o(.text) + .text 0x08000cc8 Section 0 gui_paint.o(.text) + .text 0x08001b74 Section 0 system_stm32f1xx.o(.text) + .text 0x08001c38 Section 0 stm32f1xx_hal_spi.o(.text) + SPI_WaitFlagStateUntilTimeout 0x08001d21 Thumb Code 210 stm32f1xx_hal_spi.o(.text) + SPI_EndRxTxTransaction 0x08001df3 Thumb Code 36 stm32f1xx_hal_spi.o(.text) + SPI_EndRxTransaction 0x08001fb3 Thumb Code 112 stm32f1xx_hal_spi.o(.text) + SPI_CloseTx_ISR 0x08002393 Thumb Code 130 stm32f1xx_hal_spi.o(.text) + SPI_TxISR_8BIT 0x08002415 Thumb Code 30 stm32f1xx_hal_spi.o(.text) + SPI_TxISR_16BIT 0x08002433 Thumb Code 30 stm32f1xx_hal_spi.o(.text) + SPI_CloseRx_ISR 0x080024f5 Thumb Code 76 stm32f1xx_hal_spi.o(.text) + SPI_RxISR_8BIT 0x08002541 Thumb Code 30 stm32f1xx_hal_spi.o(.text) + SPI_RxISR_16BIT 0x0800255f Thumb Code 30 stm32f1xx_hal_spi.o(.text) + SPI_CloseRxTx_ISR 0x0800257f Thumb Code 158 stm32f1xx_hal_spi.o(.text) + SPI_2linesTxISR_8BIT 0x0800261d Thumb Code 46 stm32f1xx_hal_spi.o(.text) + SPI_2linesRxISR_8BIT 0x0800264b Thumb Code 46 stm32f1xx_hal_spi.o(.text) + SPI_2linesTxISR_16BIT 0x08002679 Thumb Code 46 stm32f1xx_hal_spi.o(.text) + SPI_2linesRxISR_16BIT 0x080026a7 Thumb Code 46 stm32f1xx_hal_spi.o(.text) + SPI_DMAError 0x08002841 Thumb Code 34 stm32f1xx_hal_spi.o(.text) + SPI_DMATransmitCplt 0x08002863 Thumb Code 102 stm32f1xx_hal_spi.o(.text) + SPI_DMAHalfTransmitCplt 0x080028cb Thumb Code 10 stm32f1xx_hal_spi.o(.text) + SPI_DMAReceiveCplt 0x080029a5 Thumb Code 110 stm32f1xx_hal_spi.o(.text) + SPI_DMAHalfReceiveCplt 0x08002a15 Thumb Code 10 stm32f1xx_hal_spi.o(.text) + SPI_DMATransmitReceiveCplt 0x08002a1f Thumb Code 92 stm32f1xx_hal_spi.o(.text) + SPI_DMAHalfTransmitReceiveCplt 0x08002a7d Thumb Code 10 stm32f1xx_hal_spi.o(.text) + SPI_AbortRx_ISR 0x08002ccb Thumb Code 82 stm32f1xx_hal_spi.o(.text) + SPI_AbortTx_ISR 0x08002d1d Thumb Code 28 stm32f1xx_hal_spi.o(.text) + SPI_DMARxAbortCallback 0x08002e5d Thumb Code 98 stm32f1xx_hal_spi.o(.text) + SPI_DMATxAbortCallback 0x08002ebf Thumb Code 114 stm32f1xx_hal_spi.o(.text) + SPI_DMAAbortOnError 0x08003109 Thumb Code 16 stm32f1xx_hal_spi.o(.text) + .text 0x08003220 Section 0 stm32f1xx_hal.o(.text) + .text 0x080033a8 Section 0 stm32f1xx_hal_rcc.o(.text) + RCC_Delay 0x080034a3 Thumb Code 32 stm32f1xx_hal_rcc.o(.text) + .text 0x08003c70 Section 0 stm32f1xx_hal_gpio.o(.text) + .text 0x08004044 Section 0 stm32f1xx_hal_dma.o(.text) + DMA_SetConfig 0x08004153 Thumb Code 56 stm32f1xx_hal_dma.o(.text) + .text 0x08004c8c Section 0 stm32f1xx_hal_cortex.o(.text) + .text 0x08004eb0 Section 0 stm32f1xx_hal_uart.o(.text) + UART_SetConfig 0x08004eb1 Thumb Code 194 stm32f1xx_hal_uart.o(.text) + UART_WaitOnFlagUntilTimeout 0x08005191 Thumb Code 120 stm32f1xx_hal_uart.o(.text) + UART_EndRxTransfer 0x08005441 Thumb Code 28 stm32f1xx_hal_uart.o(.text) + UART_EndTxTransfer 0x0800545d Thumb Code 18 stm32f1xx_hal_uart.o(.text) + UART_DMAError 0x0800546f Thumb Code 74 stm32f1xx_hal_uart.o(.text) + UART_DMATxHalfCplt 0x080054bb Thumb Code 10 stm32f1xx_hal_uart.o(.text) + UART_DMATransmitCplt 0x080054c7 Thumb Code 48 stm32f1xx_hal_uart.o(.text) + UART_DMARxHalfCplt 0x08005583 Thumb Code 10 stm32f1xx_hal_uart.o(.text) + UART_DMAReceiveCplt 0x0800558f Thumb Code 62 stm32f1xx_hal_uart.o(.text) + UART_DMARxAbortCallback 0x080058c3 Thumb Code 44 stm32f1xx_hal_uart.o(.text) + UART_DMATxAbortCallback 0x080058ef Thumb Code 66 stm32f1xx_hal_uart.o(.text) + UART_DMATxOnlyAbortCallback 0x080059e5 Thumb Code 20 stm32f1xx_hal_uart.o(.text) + UART_DMARxOnlyAbortCallback 0x08005a59 Thumb Code 20 stm32f1xx_hal_uart.o(.text) + UART_EndTransmit_IT 0x08005ad5 Thumb Code 26 stm32f1xx_hal_uart.o(.text) + UART_Transmit_IT 0x08005aef Thumb Code 94 stm32f1xx_hal_uart.o(.text) + UART_DMAAbortOnError 0x08005b4d Thumb Code 16 stm32f1xx_hal_uart.o(.text) + UART_Receive_IT 0x08005b5d Thumb Code 146 stm32f1xx_hal_uart.o(.text) + .text 0x08005e4c Section 0 memseta.o(.text) + .text 0x08005e70 Section 0 uidiv.o(.text) + .text 0x08005e9c Section 36 init.o(.text) + i.__0printf$3 0x08005ec0 Section 0 printf3.o(i.__0printf$3) + i.__scatterload_copy 0x08005ee0 Section 14 handlers.o(i.__scatterload_copy) + i.__scatterload_null 0x08005eee Section 2 handlers.o(i.__scatterload_null) + i.__scatterload_zeroinit 0x08005ef0 Section 14 handlers.o(i.__scatterload_zeroinit) + i._printf_core 0x08005f00 Section 0 printf3.o(i._printf_core) + _printf_core 0x08005f01 Thumb Code 436 printf3.o(i._printf_core) + i.free 0x080060b8 Section 0 malloc.o(i.free) + i.malloc 0x08006108 Section 0 malloc.o(i.malloc) + .constdata 0x08006174 Section 10800 imagedata.o(.constdata) + .constdata 0x08008ba4 Section 714 epd_3in52.o(.constdata) + EPD_3IN52_lut_R20_GC 0x08008ba4 Data 56 epd_3in52.o(.constdata) + EPD_3IN52_lut_R21_GC 0x08008bdc Data 42 epd_3in52.o(.constdata) + EPD_3IN52_lut_R22_GC 0x08008c06 Data 56 epd_3in52.o(.constdata) + EPD_3IN52_lut_R23_GC 0x08008c3e Data 56 epd_3in52.o(.constdata) + EPD_3IN52_lut_R24_GC 0x08008c76 Data 42 epd_3in52.o(.constdata) + EPD_3IN52_lut_R20_DU 0x08008ca0 Data 56 epd_3in52.o(.constdata) + EPD_3IN52_lut_R21_DU 0x08008cd8 Data 42 epd_3in52.o(.constdata) + EPD_3IN52_lut_R22_DU 0x08008d02 Data 56 epd_3in52.o(.constdata) + EPD_3IN52_lut_R23_DU 0x08008d3a Data 56 epd_3in52.o(.constdata) + EPD_3IN52_lut_R24_DU 0x08008d72 Data 42 epd_3in52.o(.constdata) + EPD_3IN52_lut_vcom 0x08008d9c Data 42 epd_3in52.o(.constdata) + EPD_3IN52_lut_ww 0x08008dc6 Data 42 epd_3in52.o(.constdata) + EPD_3IN52_lut_bw 0x08008df0 Data 42 epd_3in52.o(.constdata) + EPD_3IN52_lut_wb 0x08008e1a Data 42 epd_3in52.o(.constdata) + EPD_3IN52_lut_bb 0x08008e44 Data 42 epd_3in52.o(.constdata) + .constdata 0x08008e6e Section 1140 font12.o(.constdata) + .constdata 0x080092e2 Section 3040 font16.o(.constdata) + .constdata 0x08009ec2 Section 16 system_stm32f1xx.o(.constdata) + .constdata 0x08009ed2 Section 8 system_stm32f1xx.o(.constdata) + .conststring 0x08009edc Section 233 gui_paint.o(.conststring) + .data 0x20000000 Section 1 epd_3in52.o(.data) + .data 0x20000004 Section 8 font12.o(.data) + .data 0x2000000c Section 8 font16.o(.data) + .data 0x20000014 Section 4 system_stm32f1xx.o(.data) + .data 0x20000018 Section 12 stm32f1xx_hal.o(.data) + .data 0x20000024 Section 4 stdout.o(.data) + .data 0x20000028 Section 4 mvars.o(.data) + .data 0x2000002c Section 4 mvars.o(.data) + .bss 0x20000030 Section 88 spi.o(.bss) + .bss 0x20000088 Section 64 usart.o(.bss) + .bss 0x200000c8 Section 24 gui_paint.o(.bss) + HEAP 0x200000e0 Section 49152 startup_stm32f103xe.o(HEAP) + STACK 0x2000c0e0 Section 4096 startup_stm32f103xe.o(STACK) Global Symbols @@ -2199,215 +922,223 @@ Image Symbol Table PendSV_Handler 0x08000409 Thumb Code 2 stm32f1xx_it.o(.text) SysTick_Handler 0x0800040b Thumb Code 4 stm32f1xx_it.o(.text) HAL_MspInit 0x08000425 Thumb Code 52 stm32f1xx_hal_msp.o(.text) - EPD_2in36g_test 0x08000461 Thumb Code 966 epd_2in36g_test.o(.text) - EPD_2IN36G_Init 0x080009d9 Thumb Code 284 epd_2in36g.o(.text) - EPD_2IN36G_Clear 0x08000af5 Thumb Code 98 epd_2in36g.o(.text) - EPD_2IN36G_Display 0x08000b57 Thumb Code 84 epd_2in36g.o(.text) - EPD_2IN36G_Sleep 0x08000bab Thumb Code 30 epd_2in36g.o(.text) - DEV_SPI_WriteByte 0x08000c85 Thumb Code 18 dev_config.o(.text) - DEV_Module_Init 0x08000c97 Thumb Code 38 dev_config.o(.text) - DEV_Module_Exit 0x08000cbd Thumb Code 38 dev_config.o(.text) - Paint_NewImage 0x08000ced Thumb Code 56 gui_paint.o(.text) - Paint_SelectImage 0x08000d25 Thumb Code 6 gui_paint.o(.text) - Paint_SetRotate 0x08000d2b Thumb Code 44 gui_paint.o(.text) - Paint_SetScale 0x08000d57 Thumb Code 80 gui_paint.o(.text) - Paint_SetMirroring 0x08000da7 Thumb Code 62 gui_paint.o(.text) - Paint_SetPixel 0x08000de5 Thumb Code 238 gui_paint.o(.text) - Paint_Clear 0x08000ed3 Thumb Code 156 gui_paint.o(.text) - Paint_ClearWindows 0x08000f6f Thumb Code 52 gui_paint.o(.text) - Paint_DrawPoint 0x08000fa3 Thumb Code 180 gui_paint.o(.text) - Paint_DrawLine 0x08001057 Thumb Code 662 gui_paint.o(.text) - Paint_DrawRectangle 0x080012ed Thumb Code 170 gui_paint.o(.text) - Paint_DrawCircle 0x08001397 Thumb Code 528 gui_paint.o(.text) - Paint_DrawChar 0x080015a7 Thumb Code 172 gui_paint.o(.text) - Paint_DrawString_EN 0x08001653 Thumb Code 116 gui_paint.o(.text) - Paint_DrawString_CN 0x080016c7 Thumb Code 518 gui_paint.o(.text) - Paint_DrawNum 0x080018cd Thumb Code 140 gui_paint.o(.text) - Paint_DrawTime 0x08001959 Thumb Code 282 gui_paint.o(.text) - Paint_DrawBitMap 0x08001a73 Thumb Code 46 gui_paint.o(.text) - Paint_DrawBitMap_Paste 0x08001aa1 Thumb Code 110 gui_paint.o(.text) - Paint_DrawBitMap_Block 0x08001b0f Thumb Code 54 gui_paint.o(.text) - SystemInit 0x08001b99 Thumb Code 60 system_stm32f1xx.o(.text) - SystemCoreClockUpdate 0x08001bd5 Thumb Code 108 system_stm32f1xx.o(.text) - HAL_SPI_Init 0x08001c5f Thumb Code 180 stm32f1xx_hal_spi.o(.text) - HAL_SPI_DeInit 0x08001d15 Thumb Code 48 stm32f1xx_hal_spi.o(.text) - HAL_SPI_Transmit 0x08001e3b Thumb Code 412 stm32f1xx_hal_spi.o(.text) - HAL_SPI_TransmitReceive 0x08002047 Thumb Code 510 stm32f1xx_hal_spi.o(.text) - HAL_SPI_Receive 0x08002245 Thumb Code 366 stm32f1xx_hal_spi.o(.text) - HAL_SPI_TxCpltCallback 0x080023b3 Thumb Code 2 stm32f1xx_hal_spi.o(.text) - HAL_SPI_ErrorCallback 0x080023b5 Thumb Code 2 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0x080032d5 Thumb Code 30 stm32f1xx_hal.o(.text) - HAL_GetTickFreq 0x080032f3 Thumb Code 6 stm32f1xx_hal.o(.text) - HAL_Delay 0x080032f9 Thumb Code 34 stm32f1xx_hal.o(.text) - HAL_SuspendTick 0x0800331b Thumb Code 14 stm32f1xx_hal.o(.text) - HAL_ResumeTick 0x08003329 Thumb Code 14 stm32f1xx_hal.o(.text) - HAL_GetHalVersion 0x08003337 Thumb Code 4 stm32f1xx_hal.o(.text) - HAL_GetREVID 0x0800333b Thumb Code 8 stm32f1xx_hal.o(.text) - HAL_GetDEVID 0x08003343 Thumb Code 10 stm32f1xx_hal.o(.text) - HAL_GetUIDw0 0x0800334d Thumb Code 6 stm32f1xx_hal.o(.text) - HAL_GetUIDw1 0x08003353 Thumb Code 6 stm32f1xx_hal.o(.text) - HAL_GetUIDw2 0x08003359 Thumb Code 6 stm32f1xx_hal.o(.text) - HAL_DBGMCU_EnableDBGSleepMode 0x0800335f Thumb Code 12 stm32f1xx_hal.o(.text) - HAL_DBGMCU_DisableDBGSleepMode 0x0800336b Thumb Code 12 stm32f1xx_hal.o(.text) - HAL_DBGMCU_EnableDBGStopMode 0x08003377 Thumb Code 12 stm32f1xx_hal.o(.text) - HAL_DBGMCU_DisableDBGStopMode 0x08003383 Thumb Code 12 stm32f1xx_hal.o(.text) - HAL_DBGMCU_EnableDBGStandbyMode 0x0800338f Thumb Code 12 stm32f1xx_hal.o(.text) - HAL_DBGMCU_DisableDBGStandbyMode 0x0800339b Thumb Code 12 stm32f1xx_hal.o(.text) - HAL_RCC_DeInit 0x080033cd Thumb Code 250 stm32f1xx_hal_rcc.o(.text) - HAL_RCC_OscConfig 0x080034e7 Thumb Code 1080 stm32f1xx_hal_rcc.o(.text) - HAL_RCC_GetSysClockFreq 0x0800391f Thumb Code 88 stm32f1xx_hal_rcc.o(.text) - HAL_RCC_ClockConfig 0x08003977 Thumb Code 364 stm32f1xx_hal_rcc.o(.text) - HAL_RCC_MCOConfig 0x08003ae3 Thumb Code 64 stm32f1xx_hal_rcc.o(.text) - HAL_RCC_EnableCSS 0x08003b23 Thumb Code 8 stm32f1xx_hal_rcc.o(.text) - HAL_RCC_DisableCSS 0x08003b2b Thumb Code 8 stm32f1xx_hal_rcc.o(.text) - HAL_RCC_GetHCLKFreq 0x08003b33 Thumb Code 6 stm32f1xx_hal_rcc.o(.text) - HAL_RCC_GetPCLK1Freq 0x08003b39 Thumb Code 22 stm32f1xx_hal_rcc.o(.text) - HAL_RCC_GetPCLK2Freq 0x08003b4f Thumb Code 22 stm32f1xx_hal_rcc.o(.text) - HAL_RCC_GetOscConfig 0x08003b65 Thumb Code 168 stm32f1xx_hal_rcc.o(.text) - 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stm32f1xx_hal_cortex.o(.text) - HAL_NVIC_SystemReset 0x08004d71 Thumb Code 26 stm32f1xx_hal_cortex.o(.text) - HAL_SYSTICK_Config 0x08004d8b Thumb Code 36 stm32f1xx_hal_cortex.o(.text) - HAL_NVIC_GetPriorityGrouping 0x08004daf Thumb Code 10 stm32f1xx_hal_cortex.o(.text) - HAL_NVIC_GetPriority 0x08004db9 Thumb Code 94 stm32f1xx_hal_cortex.o(.text) - HAL_NVIC_SetPendingIRQ 0x08004e17 Thumb Code 28 stm32f1xx_hal_cortex.o(.text) - HAL_NVIC_GetPendingIRQ 0x08004e33 Thumb Code 42 stm32f1xx_hal_cortex.o(.text) - HAL_NVIC_ClearPendingIRQ 0x08004e5d Thumb Code 28 stm32f1xx_hal_cortex.o(.text) - HAL_NVIC_GetActive 0x08004e79 Thumb Code 42 stm32f1xx_hal_cortex.o(.text) - HAL_SYSTICK_CLKSourceConfig 0x08004ea3 Thumb Code 28 stm32f1xx_hal_cortex.o(.text) - HAL_SYSTICK_Callback 0x08004ebf Thumb Code 2 stm32f1xx_hal_cortex.o(.text) - HAL_SYSTICK_IRQHandler 0x08004ec1 Thumb Code 8 stm32f1xx_hal_cortex.o(.text) - HAL_UART_Init 0x08004f99 Thumb Code 100 stm32f1xx_hal_uart.o(.text) - HAL_HalfDuplex_Init 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170 gui_paint.o(.text) + Paint_DrawCircle 0x08001373 Thumb Code 528 gui_paint.o(.text) + Paint_DrawChar 0x08001583 Thumb Code 172 gui_paint.o(.text) + Paint_DrawString_EN 0x0800162f Thumb Code 116 gui_paint.o(.text) + Paint_DrawString_CN 0x080016a3 Thumb Code 518 gui_paint.o(.text) + Paint_DrawNum 0x080018a9 Thumb Code 140 gui_paint.o(.text) + Paint_DrawTime 0x08001935 Thumb Code 282 gui_paint.o(.text) + Paint_DrawBitMap 0x08001a4f Thumb Code 46 gui_paint.o(.text) + Paint_DrawBitMap_Paste 0x08001a7d Thumb Code 110 gui_paint.o(.text) + Paint_DrawBitMap_Block 0x08001aeb Thumb Code 54 gui_paint.o(.text) + SystemInit 0x08001b75 Thumb Code 60 system_stm32f1xx.o(.text) + SystemCoreClockUpdate 0x08001bb1 Thumb Code 108 system_stm32f1xx.o(.text) + HAL_SPI_Init 0x08001c3b Thumb Code 180 stm32f1xx_hal_spi.o(.text) + HAL_SPI_DeInit 0x08001cf1 Thumb Code 48 stm32f1xx_hal_spi.o(.text) + HAL_SPI_Transmit 0x08001e17 Thumb Code 412 stm32f1xx_hal_spi.o(.text) + HAL_SPI_TransmitReceive 0x08002023 Thumb Code 510 stm32f1xx_hal_spi.o(.text) + HAL_SPI_Receive 0x08002221 Thumb Code 366 stm32f1xx_hal_spi.o(.text) + HAL_SPI_TxCpltCallback 0x0800238f Thumb Code 2 stm32f1xx_hal_spi.o(.text) + HAL_SPI_ErrorCallback 0x08002391 Thumb Code 2 stm32f1xx_hal_spi.o(.text) + HAL_SPI_Transmit_IT 0x08002451 Thumb Code 162 stm32f1xx_hal_spi.o(.text) + HAL_SPI_RxCpltCallback 0x080024f3 Thumb Code 2 stm32f1xx_hal_spi.o(.text) + HAL_SPI_TxRxCpltCallback 0x0800257d Thumb Code 2 stm32f1xx_hal_spi.o(.text) + HAL_SPI_TransmitReceive_IT 0x080026d5 Thumb Code 188 stm32f1xx_hal_spi.o(.text) + HAL_SPI_Receive_IT 0x08002791 Thumb Code 176 stm32f1xx_hal_spi.o(.text) + HAL_SPI_TxHalfCpltCallback 0x080028c9 Thumb Code 2 stm32f1xx_hal_spi.o(.text) + HAL_SPI_Transmit_DMA 0x080028d5 Thumb Code 208 stm32f1xx_hal_spi.o(.text) + HAL_SPI_RxHalfCpltCallback 0x08002a13 Thumb Code 2 stm32f1xx_hal_spi.o(.text) + HAL_SPI_TxRxHalfCpltCallback 0x08002a7b Thumb Code 2 stm32f1xx_hal_spi.o(.text) + HAL_SPI_TransmitReceive_DMA 0x08002a87 Thumb Code 302 stm32f1xx_hal_spi.o(.text) + HAL_SPI_Receive_DMA 0x08002bb5 Thumb Code 278 stm32f1xx_hal_spi.o(.text) + HAL_SPI_Abort 0x08002d39 Thumb Code 290 stm32f1xx_hal_spi.o(.text) + HAL_SPI_AbortCpltCallback 0x08002e5b Thumb Code 2 stm32f1xx_hal_spi.o(.text) + HAL_SPI_Abort_IT 0x08002f31 Thumb Code 328 stm32f1xx_hal_spi.o(.text) + HAL_SPI_DMAPause 0x08003079 Thumb Code 38 stm32f1xx_hal_spi.o(.text) + HAL_SPI_DMAResume 0x0800309f Thumb Code 38 stm32f1xx_hal_spi.o(.text) + HAL_SPI_DMAStop 0x080030c5 Thumb Code 68 stm32f1xx_hal_spi.o(.text) + HAL_SPI_IRQHandler 0x08003119 Thumb Code 250 stm32f1xx_hal_spi.o(.text) + HAL_SPI_GetState 0x08003213 Thumb Code 6 stm32f1xx_hal_spi.o(.text) + HAL_SPI_GetError 0x08003219 Thumb Code 4 stm32f1xx_hal_spi.o(.text) + HAL_InitTick 0x08003223 Thumb Code 58 stm32f1xx_hal.o(.text) + HAL_Init 0x0800325d Thumb Code 32 stm32f1xx_hal.o(.text) + HAL_MspDeInit 0x0800327d Thumb Code 2 stm32f1xx_hal.o(.text) + HAL_DeInit 0x0800327f Thumb Code 26 stm32f1xx_hal.o(.text) + HAL_IncTick 0x08003299 Thumb Code 12 stm32f1xx_hal.o(.text) + HAL_GetTick 0x080032a5 Thumb Code 6 stm32f1xx_hal.o(.text) + HAL_GetTickPrio 0x080032ab Thumb Code 6 stm32f1xx_hal.o(.text) + HAL_SetTickFreq 0x080032b1 Thumb Code 30 stm32f1xx_hal.o(.text) + HAL_GetTickFreq 0x080032cf Thumb Code 6 stm32f1xx_hal.o(.text) + HAL_Delay 0x080032d5 Thumb Code 34 stm32f1xx_hal.o(.text) + HAL_SuspendTick 0x080032f7 Thumb Code 14 stm32f1xx_hal.o(.text) + HAL_ResumeTick 0x08003305 Thumb Code 14 stm32f1xx_hal.o(.text) + HAL_GetHalVersion 0x08003313 Thumb Code 4 stm32f1xx_hal.o(.text) + HAL_GetREVID 0x08003317 Thumb Code 8 stm32f1xx_hal.o(.text) + HAL_GetDEVID 0x0800331f Thumb Code 10 stm32f1xx_hal.o(.text) + HAL_GetUIDw0 0x08003329 Thumb Code 6 stm32f1xx_hal.o(.text) + HAL_GetUIDw1 0x0800332f Thumb Code 6 stm32f1xx_hal.o(.text) + HAL_GetUIDw2 0x08003335 Thumb Code 6 stm32f1xx_hal.o(.text) + HAL_DBGMCU_EnableDBGSleepMode 0x0800333b Thumb Code 12 stm32f1xx_hal.o(.text) + HAL_DBGMCU_DisableDBGSleepMode 0x08003347 Thumb Code 12 stm32f1xx_hal.o(.text) + HAL_DBGMCU_EnableDBGStopMode 0x08003353 Thumb Code 12 stm32f1xx_hal.o(.text) + HAL_DBGMCU_DisableDBGStopMode 0x0800335f Thumb Code 12 stm32f1xx_hal.o(.text) + HAL_DBGMCU_EnableDBGStandbyMode 0x0800336b Thumb Code 12 stm32f1xx_hal.o(.text) + HAL_DBGMCU_DisableDBGStandbyMode 0x08003377 Thumb Code 12 stm32f1xx_hal.o(.text) + HAL_RCC_DeInit 0x080033a9 Thumb Code 250 stm32f1xx_hal_rcc.o(.text) + HAL_RCC_OscConfig 0x080034c3 Thumb Code 1080 stm32f1xx_hal_rcc.o(.text) + HAL_RCC_GetSysClockFreq 0x080038fb Thumb Code 88 stm32f1xx_hal_rcc.o(.text) + HAL_RCC_ClockConfig 0x08003953 Thumb Code 364 stm32f1xx_hal_rcc.o(.text) + HAL_RCC_MCOConfig 0x08003abf Thumb Code 64 stm32f1xx_hal_rcc.o(.text) + HAL_RCC_EnableCSS 0x08003aff Thumb Code 8 stm32f1xx_hal_rcc.o(.text) + HAL_RCC_DisableCSS 0x08003b07 Thumb Code 8 stm32f1xx_hal_rcc.o(.text) + HAL_RCC_GetHCLKFreq 0x08003b0f Thumb Code 6 stm32f1xx_hal_rcc.o(.text) + HAL_RCC_GetPCLK1Freq 0x08003b15 Thumb Code 22 stm32f1xx_hal_rcc.o(.text) + HAL_RCC_GetPCLK2Freq 0x08003b2b Thumb Code 22 stm32f1xx_hal_rcc.o(.text) + HAL_RCC_GetOscConfig 0x08003b41 Thumb Code 168 stm32f1xx_hal_rcc.o(.text) + HAL_RCC_GetClockConfig 0x08003be9 Thumb Code 52 stm32f1xx_hal_rcc.o(.text) + HAL_RCC_CSSCallback 0x08003c1d Thumb Code 2 stm32f1xx_hal_rcc.o(.text) + HAL_RCC_NMI_IRQHandler 0x08003c1f Thumb Code 22 stm32f1xx_hal_rcc.o(.text) + HAL_GPIO_Init 0x08003c71 Thumb Code 524 stm32f1xx_hal_gpio.o(.text) + HAL_GPIO_DeInit 0x08003e7d Thumb Code 320 stm32f1xx_hal_gpio.o(.text) + HAL_GPIO_ReadPin 0x08003fbd Thumb Code 14 stm32f1xx_hal_gpio.o(.text) + HAL_GPIO_WritePin 0x08003fcb Thumb Code 14 stm32f1xx_hal_gpio.o(.text) + HAL_GPIO_TogglePin 0x08003fd9 Thumb Code 16 stm32f1xx_hal_gpio.o(.text) + HAL_GPIO_LockPin 0x08003fe9 Thumb Code 42 stm32f1xx_hal_gpio.o(.text) + HAL_GPIO_EXTI_Callback 0x08004013 Thumb Code 2 stm32f1xx_hal_gpio.o(.text) + HAL_GPIO_EXTI_IRQHandler 0x08004015 Thumb Code 18 stm32f1xx_hal_gpio.o(.text) + HAL_DMA_Init 0x08004045 Thumb Code 144 stm32f1xx_hal_dma.o(.text) + HAL_DMA_DeInit 0x080040d5 Thumb Code 126 stm32f1xx_hal_dma.o(.text) + HAL_DMA_Start 0x0800418b Thumb Code 88 stm32f1xx_hal_dma.o(.text) + HAL_DMA_Start_IT 0x080041e3 Thumb Code 124 stm32f1xx_hal_dma.o(.text) + HAL_DMA_Abort 0x0800425f Thumb Code 72 stm32f1xx_hal_dma.o(.text) + HAL_DMA_Abort_IT 0x080042a7 Thumb Code 318 stm32f1xx_hal_dma.o(.text) + HAL_DMA_PollForTransfer 0x080043e5 Thumb Code 1316 stm32f1xx_hal_dma.o(.text) + HAL_DMA_IRQHandler 0x08004909 Thumb Code 672 stm32f1xx_hal_dma.o(.text) + HAL_DMA_RegisterCallback 0x08004ba9 Thumb Code 80 stm32f1xx_hal_dma.o(.text) + HAL_DMA_UnRegisterCallback 0x08004bf9 Thumb Code 86 stm32f1xx_hal_dma.o(.text) + HAL_DMA_GetState 0x08004c4f Thumb Code 6 stm32f1xx_hal_dma.o(.text) + HAL_DMA_GetError 0x08004c55 Thumb Code 4 stm32f1xx_hal_dma.o(.text) + HAL_NVIC_SetPriorityGrouping 0x08004c8d Thumb Code 30 stm32f1xx_hal_cortex.o(.text) + HAL_NVIC_SetPriority 0x08004cab Thumb Code 98 stm32f1xx_hal_cortex.o(.text) + HAL_NVIC_EnableIRQ 0x08004d0d Thumb Code 28 stm32f1xx_hal_cortex.o(.text) + HAL_NVIC_DisableIRQ 0x08004d29 Thumb Code 36 stm32f1xx_hal_cortex.o(.text) + HAL_NVIC_SystemReset 0x08004d4d Thumb Code 26 stm32f1xx_hal_cortex.o(.text) + HAL_SYSTICK_Config 0x08004d67 Thumb Code 36 stm32f1xx_hal_cortex.o(.text) + HAL_NVIC_GetPriorityGrouping 0x08004d8b Thumb Code 10 stm32f1xx_hal_cortex.o(.text) + HAL_NVIC_GetPriority 0x08004d95 Thumb Code 94 stm32f1xx_hal_cortex.o(.text) + HAL_NVIC_SetPendingIRQ 0x08004df3 Thumb Code 28 stm32f1xx_hal_cortex.o(.text) + HAL_NVIC_GetPendingIRQ 0x08004e0f Thumb Code 42 stm32f1xx_hal_cortex.o(.text) + HAL_NVIC_ClearPendingIRQ 0x08004e39 Thumb Code 28 stm32f1xx_hal_cortex.o(.text) + HAL_NVIC_GetActive 0x08004e55 Thumb Code 42 stm32f1xx_hal_cortex.o(.text) + HAL_SYSTICK_CLKSourceConfig 0x08004e7f Thumb Code 28 stm32f1xx_hal_cortex.o(.text) + HAL_SYSTICK_Callback 0x08004e9b Thumb Code 2 stm32f1xx_hal_cortex.o(.text) + HAL_SYSTICK_IRQHandler 0x08004e9d Thumb Code 8 stm32f1xx_hal_cortex.o(.text) + HAL_UART_Init 0x08004f75 Thumb Code 100 stm32f1xx_hal_uart.o(.text) + HAL_HalfDuplex_Init 0x08004fd9 Thumb Code 110 stm32f1xx_hal_uart.o(.text) + HAL_LIN_Init 0x08005047 Thumb Code 130 stm32f1xx_hal_uart.o(.text) + HAL_MultiProcessor_Init 0x080050c9 Thumb Code 146 stm32f1xx_hal_uart.o(.text) + HAL_UART_DeInit 0x0800515d Thumb Code 52 stm32f1xx_hal_uart.o(.text) + HAL_UART_Transmit 0x08005209 Thumb Code 202 stm32f1xx_hal_uart.o(.text) + HAL_UART_Receive 0x080052d3 Thumb Code 212 stm32f1xx_hal_uart.o(.text) + HAL_UART_Transmit_IT 0x080053a7 Thumb Code 66 stm32f1xx_hal_uart.o(.text) + HAL_UART_Receive_IT 0x080053e9 Thumb Code 86 stm32f1xx_hal_uart.o(.text) + HAL_UART_ErrorCallback 0x0800543f Thumb Code 2 stm32f1xx_hal_uart.o(.text) + HAL_UART_TxHalfCpltCallback 0x080054b9 Thumb Code 2 stm32f1xx_hal_uart.o(.text) + HAL_UART_TxCpltCallback 0x080054c5 Thumb Code 2 stm32f1xx_hal_uart.o(.text) + HAL_UART_Transmit_DMA 0x080054f7 Thumb Code 138 stm32f1xx_hal_uart.o(.text) + HAL_UART_RxHalfCpltCallback 0x08005581 Thumb Code 2 stm32f1xx_hal_uart.o(.text) + HAL_UART_RxCpltCallback 0x0800558d Thumb Code 2 stm32f1xx_hal_uart.o(.text) + HAL_UART_Receive_DMA 0x080055cd Thumb Code 150 stm32f1xx_hal_uart.o(.text) + HAL_UART_DMAPause 0x08005663 Thumb Code 102 stm32f1xx_hal_uart.o(.text) + HAL_UART_DMAResume 0x080056c9 Thumb Code 98 stm32f1xx_hal_uart.o(.text) + HAL_UART_DMAStop 0x0800572b Thumb Code 88 stm32f1xx_hal_uart.o(.text) + HAL_UART_Abort 0x08005783 Thumb Code 148 stm32f1xx_hal_uart.o(.text) + HAL_UART_AbortTransmit 0x08005817 Thumb Code 80 stm32f1xx_hal_uart.o(.text) + HAL_UART_AbortReceive 0x08005867 Thumb Code 90 stm32f1xx_hal_uart.o(.text) + HAL_UART_AbortCpltCallback 0x080058c1 Thumb Code 2 stm32f1xx_hal_uart.o(.text) + HAL_UART_Abort_IT 0x08005931 Thumb Code 178 stm32f1xx_hal_uart.o(.text) + HAL_UART_AbortTransmitCpltCallback 0x080059e3 Thumb Code 2 stm32f1xx_hal_uart.o(.text) + HAL_UART_AbortTransmit_IT 0x080059f9 Thumb Code 94 stm32f1xx_hal_uart.o(.text) + HAL_UART_AbortReceiveCpltCallback 0x08005a57 Thumb Code 2 stm32f1xx_hal_uart.o(.text) + HAL_UART_AbortReceive_IT 0x08005a6d Thumb Code 104 stm32f1xx_hal_uart.o(.text) + HAL_UART_IRQHandler 0x08005bef Thumb Code 312 stm32f1xx_hal_uart.o(.text) + HAL_LIN_SendBreak 0x08005d27 Thumb Code 70 stm32f1xx_hal_uart.o(.text) + HAL_MultiProcessor_EnterMuteMode 0x08005d6d Thumb Code 50 stm32f1xx_hal_uart.o(.text) + HAL_MultiProcessor_ExitMuteMode 0x08005d9f Thumb Code 50 stm32f1xx_hal_uart.o(.text) + HAL_HalfDuplex_EnableTransmitter 0x08005dd1 Thumb Code 54 stm32f1xx_hal_uart.o(.text) + HAL_HalfDuplex_EnableReceiver 0x08005e07 Thumb Code 54 stm32f1xx_hal_uart.o(.text) + HAL_UART_GetState 0x08005e3d Thumb Code 12 stm32f1xx_hal_uart.o(.text) + HAL_UART_GetError 0x08005e49 Thumb Code 4 stm32f1xx_hal_uart.o(.text) + __aeabi_memset 0x08005e4d Thumb Code 14 memseta.o(.text) + __aeabi_memset4 0x08005e4d Thumb Code 0 memseta.o(.text) + __aeabi_memset8 0x08005e4d Thumb Code 0 memseta.o(.text) + __aeabi_memclr 0x08005e5b Thumb Code 4 memseta.o(.text) + __aeabi_memclr4 0x08005e5b Thumb Code 0 memseta.o(.text) + __aeabi_memclr8 0x08005e5b Thumb Code 0 memseta.o(.text) + _memset$wrapper 0x08005e5f Thumb Code 18 memseta.o(.text) + __aeabi_uidiv 0x08005e71 Thumb Code 0 uidiv.o(.text) + __aeabi_uidivmod 0x08005e71 Thumb Code 44 uidiv.o(.text) + __scatterload 0x08005e9d Thumb Code 28 init.o(.text) + __scatterload_rt2 0x08005e9d Thumb Code 0 init.o(.text) + __0printf$3 0x08005ec1 Thumb Code 22 printf3.o(i.__0printf$3) + __1printf$3 0x08005ec1 Thumb Code 0 printf3.o(i.__0printf$3) + __2printf 0x08005ec1 Thumb Code 0 printf3.o(i.__0printf$3) + __scatterload_copy 0x08005ee1 Thumb Code 14 handlers.o(i.__scatterload_copy) + __scatterload_null 0x08005eef Thumb Code 2 handlers.o(i.__scatterload_null) + __scatterload_zeroinit 0x08005ef1 Thumb Code 14 handlers.o(i.__scatterload_zeroinit) + free 0x080060b9 Thumb Code 76 malloc.o(i.free) + malloc 0x08006109 Thumb Code 92 malloc.o(i.malloc) + gImage_3in52 0x08006174 Data 10800 imagedata.o(.constdata) + Font12_Table 0x08008e6e Data 1140 font12.o(.constdata) + Font16_Table 0x080092e2 Data 3040 font16.o(.constdata) + AHBPrescTable 0x08009ec2 Data 16 system_stm32f1xx.o(.constdata) + APBPrescTable 0x08009ed2 Data 8 system_stm32f1xx.o(.constdata) + Region$$Table$$Base 0x08009fc8 Number 0 anon$$obj.o(Region$$Table) + Region$$Table$$Limit 0x08009fe8 Number 0 anon$$obj.o(Region$$Table) + EPD_3IN52_Flag 0x20000000 Data 1 epd_3in52.o(.data) + Font12 0x20000004 Data 8 font12.o(.data) + Font16 0x2000000c Data 8 font16.o(.data) + SystemCoreClock 0x20000014 Data 4 system_stm32f1xx.o(.data) + uwTickFreq 0x20000018 Data 1 stm32f1xx_hal.o(.data) + uwTickPrio 0x2000001c Data 4 stm32f1xx_hal.o(.data) + uwTick 0x20000020 Data 4 stm32f1xx_hal.o(.data) + __stdout 0x20000024 Data 4 stdout.o(.data) + __microlib_freelist 0x20000028 Data 4 mvars.o(.data) + __microlib_freelist_initialised 0x2000002c Data 4 mvars.o(.data) + hspi1 0x20000030 Data 88 spi.o(.bss) + huart1 0x20000088 Data 64 usart.o(.bss) + Paint 0x200000c8 Data 24 gui_paint.o(.bss) + __heap_base 0x200000e0 Data 0 startup_stm32f103xe.o(HEAP) + __heap_limit 0x2000c0e0 Data 0 startup_stm32f103xe.o(HEAP) + __initial_sp 0x2000d0e0 Data 0 startup_stm32f103xe.o(STACK) @@ -2417,22 +1148,22 @@ Memory Map of the image Image Entry point : 0x08000131 - Load Region LR_IROM1 (Base: 0x08000000, Size: 0x0000b55c, Max: 0x00080000, ABSOLUTE) + Load Region LR_IROM1 (Base: 0x08000000, Size: 0x0000a018, Max: 0x00080000, ABSOLUTE) - Execution Region ER_IROM1 (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x0000b524, Max: 0x00080000, ABSOLUTE) + Execution Region ER_IROM1 (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x00009fe8, Max: 0x00080000, ABSOLUTE) Exec Addr Load Addr Size Type Attr Idx E Section Name Object 0x08000000 0x08000000 0x00000130 Data RO 3 RESET startup_stm32f103xe.o - 0x08000130 0x08000130 0x00000000 Code RO 3303 * .ARM.Collect$$$$00000000 mc_w.l(entry.o) - 0x08000130 0x08000130 0x00000004 Code RO 3603 .ARM.Collect$$$$00000001 mc_w.l(entry2.o) - 0x08000134 0x08000134 0x00000004 Code RO 3606 .ARM.Collect$$$$00000004 mc_w.l(entry5.o) - 0x08000138 0x08000138 0x00000000 Code RO 3608 .ARM.Collect$$$$00000008 mc_w.l(entry7b.o) - 0x08000138 0x08000138 0x00000000 Code RO 3610 .ARM.Collect$$$$0000000A mc_w.l(entry8b.o) - 0x08000138 0x08000138 0x00000008 Code RO 3611 .ARM.Collect$$$$0000000B mc_w.l(entry9a.o) - 0x08000140 0x08000140 0x00000000 Code RO 3613 .ARM.Collect$$$$0000000D mc_w.l(entry10a.o) - 0x08000140 0x08000140 0x00000000 Code RO 3615 .ARM.Collect$$$$0000000F mc_w.l(entry11a.o) - 0x08000140 0x08000140 0x00000004 Code RO 3604 .ARM.Collect$$$$00002712 mc_w.l(entry2.o) + 0x08000130 0x08000130 0x00000000 Code RO 970 * .ARM.Collect$$$$00000000 mc_w.l(entry.o) + 0x08000130 0x08000130 0x00000004 Code RO 1266 .ARM.Collect$$$$00000001 mc_w.l(entry2.o) + 0x08000134 0x08000134 0x00000004 Code RO 1269 .ARM.Collect$$$$00000004 mc_w.l(entry5.o) + 0x08000138 0x08000138 0x00000000 Code RO 1271 .ARM.Collect$$$$00000008 mc_w.l(entry7b.o) + 0x08000138 0x08000138 0x00000000 Code RO 1273 .ARM.Collect$$$$0000000A mc_w.l(entry8b.o) + 0x08000138 0x08000138 0x00000008 Code RO 1274 .ARM.Collect$$$$0000000B mc_w.l(entry9a.o) + 0x08000140 0x08000140 0x00000000 Code RO 1276 .ARM.Collect$$$$0000000D mc_w.l(entry10a.o) + 0x08000140 0x08000140 0x00000000 Code RO 1278 .ARM.Collect$$$$0000000F mc_w.l(entry11a.o) + 0x08000140 0x08000140 0x00000004 Code RO 1267 .ARM.Collect$$$$00002712 mc_w.l(entry2.o) 0x08000144 0x08000144 0x00000024 Code RO 4 .text startup_stm32f103xe.o 0x08000168 0x08000168 0x00000098 Code RO 13 .text main.o 0x08000200 0x08000200 0x00000060 Code RO 162 .text gpio.o @@ -2440,58 +1171,59 @@ Memory Map of the image 0x0800031c 0x0800031c 0x000000d8 Code RO 216 .text usart.o 0x080003f4 0x080003f4 0x00000030 Code RO 246 .text stm32f1xx_it.o 0x08000424 0x08000424 0x0000003c Code RO 273 .text stm32f1xx_hal_msp.o - 0x08000460 0x08000460 0x00000550 Code RO 1569 .text epd_2in36g_test.o - 0x080009b0 0x080009b0 0x000002d4 Code RO 2729 .text epd_2in36g.o - 0x08000c84 0x08000c84 0x00000068 Code RO 2753 .text dev_config.o - 0x08000cec 0x08000cec 0x00000eac Code RO 2778 .text gui_paint.o - 0x08001b98 0x08001b98 0x000000c4 Code RO 2912 .text system_stm32f1xx.o - 0x08001c5c 0x08001c5c 0x000015e8 Code RO 2968 .text stm32f1xx_hal_spi.o - 0x08003244 0x08003244 0x00000188 Code RO 2992 .text stm32f1xx_hal.o - 0x080033cc 0x080033cc 0x000008c8 Code RO 3022 .text stm32f1xx_hal_rcc.o - 0x08003c94 0x08003c94 0x000003d4 Code RO 3070 .text stm32f1xx_hal_gpio.o - 0x08004068 0x08004068 0x00000c48 Code RO 3094 .text stm32f1xx_hal_dma.o - 0x08004cb0 0x08004cb0 0x00000224 Code RO 3118 .text stm32f1xx_hal_cortex.o - 0x08004ed4 0x08004ed4 0x00000f9c Code RO 3282 .text stm32f1xx_hal_uart.o - 0x08005e70 0x08005e70 0x00000024 Code RO 3310 .text mc_w.l(memseta.o) - 0x08005e94 0x08005e94 0x0000002c Code RO 3618 .text mc_w.l(uidiv.o) - 0x08005ec0 0x08005ec0 0x00000024 Code RO 3635 .text mc_w.l(init.o) - 0x08005ee4 0x08005ee4 0x00000020 Code RO 3403 i.__0printf$3 mc_w.l(printf3.o) - 0x08005f04 0x08005f04 0x0000000e Code RO 3645 i.__scatterload_copy mc_w.l(handlers.o) - 0x08005f12 0x08005f12 0x00000002 Code RO 3646 i.__scatterload_null mc_w.l(handlers.o) - 0x08005f14 0x08005f14 0x0000000e Code RO 3647 i.__scatterload_zeroinit mc_w.l(handlers.o) - 0x08005f22 0x08005f22 0x00000002 PAD - 0x08005f24 0x08005f24 0x000001b8 Code RO 3410 i._printf_core mc_w.l(printf3.o) - 0x080060dc 0x080060dc 0x00000050 Code RO 3575 i.free mc_w.l(malloc.o) - 0x0800612c 0x0800612c 0x0000006c Code RO 3576 i.malloc mc_w.l(malloc.o) - 0x08006198 0x08006198 0x00003090 Data RO 354 .constdata imagedata2.o - 0x08009228 0x08009228 0x00000474 Data RO 2825 .constdata font12.o - 0x0800969c 0x0800969c 0x00000be0 Data RO 2853 .constdata font16.o - 0x0800a27c 0x0800a27c 0x00001182 Data RO 2895 .constdata font24cn.o - 0x0800b3fe 0x0800b3fe 0x00000010 Data RO 2913 .constdata system_stm32f1xx.o - 0x0800b40e 0x0800b40e 0x00000008 Data RO 2914 .constdata system_stm32f1xx.o - 0x0800b416 0x0800b416 0x00000002 PAD - 0x0800b418 0x0800b418 0x000000e9 Data RO 2780 .conststring gui_paint.o - 0x0800b501 0x0800b501 0x00000003 PAD - 0x0800b504 0x0800b504 0x00000020 Data RO 3643 Region$$Table anon$$obj.o + 0x08000460 0x08000460 0x00000334 Code RO 354 .text epd_3in52_test.o + 0x08000794 0x08000794 0x000004cc Code RO 385 .text epd_3in52.o + 0x08000c60 0x08000c60 0x00000068 Code RO 417 .text dev_config.o + 0x08000cc8 0x08000cc8 0x00000eac Code RO 442 .text gui_paint.o + 0x08001b74 0x08001b74 0x000000c4 Code RO 579 .text system_stm32f1xx.o + 0x08001c38 0x08001c38 0x000015e8 Code RO 635 .text stm32f1xx_hal_spi.o + 0x08003220 0x08003220 0x00000188 Code RO 659 .text stm32f1xx_hal.o + 0x080033a8 0x080033a8 0x000008c8 Code RO 689 .text stm32f1xx_hal_rcc.o + 0x08003c70 0x08003c70 0x000003d4 Code RO 737 .text stm32f1xx_hal_gpio.o + 0x08004044 0x08004044 0x00000c48 Code RO 761 .text stm32f1xx_hal_dma.o + 0x08004c8c 0x08004c8c 0x00000224 Code RO 785 .text stm32f1xx_hal_cortex.o + 0x08004eb0 0x08004eb0 0x00000f9c Code RO 949 .text stm32f1xx_hal_uart.o + 0x08005e4c 0x08005e4c 0x00000024 Code RO 975 .text mc_w.l(memseta.o) + 0x08005e70 0x08005e70 0x0000002c Code RO 1281 .text mc_w.l(uidiv.o) + 0x08005e9c 0x08005e9c 0x00000024 Code RO 1302 .text mc_w.l(init.o) + 0x08005ec0 0x08005ec0 0x00000020 Code RO 1066 i.__0printf$3 mc_w.l(printf3.o) + 0x08005ee0 0x08005ee0 0x0000000e Code RO 1312 i.__scatterload_copy mc_w.l(handlers.o) + 0x08005eee 0x08005eee 0x00000002 Code RO 1313 i.__scatterload_null mc_w.l(handlers.o) + 0x08005ef0 0x08005ef0 0x0000000e Code RO 1314 i.__scatterload_zeroinit mc_w.l(handlers.o) + 0x08005efe 0x08005efe 0x00000002 PAD + 0x08005f00 0x08005f00 0x000001b8 Code RO 1073 i._printf_core mc_w.l(printf3.o) + 0x080060b8 0x080060b8 0x00000050 Code RO 1238 i.free mc_w.l(malloc.o) + 0x08006108 0x08006108 0x0000006c Code RO 1239 i.malloc mc_w.l(malloc.o) + 0x08006174 0x08006174 0x00002a30 Data RO 319 .constdata imagedata.o + 0x08008ba4 0x08008ba4 0x000002ca Data RO 386 .constdata epd_3in52.o + 0x08008e6e 0x08008e6e 0x00000474 Data RO 492 .constdata font12.o + 0x080092e2 0x080092e2 0x00000be0 Data RO 520 .constdata font16.o + 0x08009ec2 0x08009ec2 0x00000010 Data RO 580 .constdata system_stm32f1xx.o + 0x08009ed2 0x08009ed2 0x00000008 Data RO 581 .constdata system_stm32f1xx.o + 0x08009eda 0x08009eda 0x00000002 PAD + 0x08009edc 0x08009edc 0x000000e9 Data RO 444 .conststring gui_paint.o + 0x08009fc5 0x08009fc5 0x00000003 PAD + 0x08009fc8 0x08009fc8 0x00000020 Data RO 1310 Region$$Table anon$$obj.o - Execution Region RW_IRAM1 (Exec base: 0x20000000, Load base: 0x0800b524, Size: 0x0000d0e8, Max: 0x00010000, ABSOLUTE) + Execution Region RW_IRAM1 (Exec base: 0x20000000, Load base: 0x08009fe8, Size: 0x0000d0e0, Max: 0x00010000, ABSOLUTE) Exec Addr Load Addr Size Type Attr Idx E Section Name Object - 0x20000000 0x0800b524 0x00000008 Data RW 2826 .data font12.o - 0x20000008 0x0800b52c 0x00000008 Data RW 2854 .data font16.o - 0x20000010 0x0800b534 0x0000000c Data RW 2896 .data font24cn.o - 0x2000001c 0x0800b540 0x00000004 Data RW 2915 .data system_stm32f1xx.o - 0x20000020 0x0800b544 0x0000000c Data RW 2993 .data stm32f1xx_hal.o - 0x2000002c 0x0800b550 0x00000004 Data RW 3617 .data mc_w.l(stdout.o) - 0x20000030 0x0800b554 0x00000004 Data RW 3622 .data mc_w.l(mvars.o) - 0x20000034 0x0800b558 0x00000004 Data RW 3623 .data mc_w.l(mvars.o) - 0x20000038 - 0x00000058 Zero RW 187 .bss spi.o - 0x20000090 - 0x00000040 Zero RW 217 .bss usart.o - 0x200000d0 - 0x00000018 Zero RW 2779 .bss gui_paint.o - 0x200000e8 - 0x0000c000 Zero RW 2 HEAP startup_stm32f103xe.o - 0x2000c0e8 - 0x00001000 Zero RW 1 STACK startup_stm32f103xe.o + 0x20000000 0x08009fe8 0x00000001 Data RW 387 .data epd_3in52.o + 0x20000001 0x08009fe9 0x00000003 PAD + 0x20000004 0x08009fec 0x00000008 Data RW 493 .data font12.o + 0x2000000c 0x08009ff4 0x00000008 Data RW 521 .data font16.o + 0x20000014 0x08009ffc 0x00000004 Data RW 582 .data system_stm32f1xx.o + 0x20000018 0x0800a000 0x0000000c Data RW 660 .data stm32f1xx_hal.o + 0x20000024 0x0800a00c 0x00000004 Data RW 1280 .data mc_w.l(stdout.o) + 0x20000028 0x0800a010 0x00000004 Data RW 1289 .data mc_w.l(mvars.o) + 0x2000002c 0x0800a014 0x00000004 Data RW 1290 .data mc_w.l(mvars.o) + 0x20000030 - 0x00000058 Zero RW 187 .bss spi.o + 0x20000088 - 0x00000040 Zero RW 217 .bss usart.o + 0x200000c8 - 0x00000018 Zero RW 443 .bss gui_paint.o + 0x200000e0 - 0x0000c000 Zero RW 2 HEAP startup_stm32f103xe.o + 0x2000c0e0 - 0x00001000 Zero RW 1 STACK startup_stm32f103xe.o ============================================================================== @@ -2502,15 +1234,14 @@ Image component sizes Code (inc. data) RO Data RW Data ZI Data Debug Object Name 104 10 0 0 0 792 dev_config.o - 724 60 0 0 0 2711 epd_2in36g.o - 1360 394 0 0 0 1718 epd_2in36g_test.o + 1228 76 714 1 0 4838 epd_3in52.o + 820 306 0 0 0 1259 epd_3in52_test.o 0 0 1140 8 0 1389 font12.o 0 0 3040 8 0 1389 font16.o - 0 0 4482 12 0 1391 font24cn.o 96 10 0 0 0 827 gpio.o 3756 662 233 0 24 14644 gui_paint.o - 0 0 12432 0 0 920 imagedata2.o - 152 20 0 0 0 462020 main.o + 0 0 10800 0 0 3193 imagedata.o + 152 20 0 0 0 462016 main.o 188 18 0 0 88 1473 spi.o 36 8 304 0 53248 804 startup_stm32f103xe.o 392 38 0 12 0 7697 stm32f1xx_hal.o @@ -2526,9 +1257,9 @@ Image component sizes 216 18 0 0 64 1777 usart.o ---------------------------------------------------------------------- - 23852 1742 21692 44 53424 589163 Object Totals + 23816 1670 16292 36 53424 591709 Object Totals 0 0 32 0 0 0 (incl. Generated) - 0 0 5 0 0 0 (incl. Padding) + 0 0 5 3 0 0 (incl. Padding) ---------------------------------------------------------------------- @@ -2571,15 +1302,15 @@ Image component sizes Code (inc. data) RO Data RW Data ZI Data Debug - 24680 1792 21692 56 53424 588043 Grand Totals - 24680 1792 21692 56 53424 588043 ELF Image Totals - 24680 1792 21692 56 0 0 ROM Totals + 24644 1720 16292 48 53424 590589 Grand Totals + 24644 1720 16292 48 53424 590589 ELF Image Totals + 24644 1720 16292 48 0 0 ROM Totals ============================================================================== - Total RO Size (Code + RO Data) 46372 ( 45.29kB) - Total RW Size (RW Data + ZI Data) 53480 ( 52.23kB) - Total ROM Size (Code + RO Data + RW Data) 46428 ( 45.34kB) + Total RO Size (Code + RO Data) 40936 ( 39.98kB) + Total RW Size (RW Data + ZI Data) 53472 ( 52.22kB) + Total ROM Size (Code + RO Data + RW Data) 40984 ( 40.02kB) ============================================================================== diff --git a/STM32/STM32-F103ZET6/MDK-ARM/startup_stm32f103xe.lst b/STM32/STM32-F103ZET6/MDK-ARM/startup_stm32f103xe.lst deleted file mode 100644 index f3a5f23..0000000 --- a/STM32/STM32-F103ZET6/MDK-ARM/startup_stm32f103xe.lst +++ /dev/null @@ -1,1465 +0,0 @@ - - - -ARM Macro Assembler Page 1 - - - 1 00000000 ;******************** (C) COPYRIGHT 2017 STMicroelectron - ics ******************** - 2 00000000 ;* File Name : startup_stm32f103xe.s - 3 00000000 ;* Author : MCD Application Team - 4 00000000 ;* Version : V4.2.0 - 5 00000000 ;* Date : 31-March-2017 - 6 00000000 ;* Description : STM32F103xE Devices vector table - for MDK-ARM toolchain. - 7 00000000 ;* This module performs: - 8 00000000 ;* - Set the initial SP - 9 00000000 ;* - Set the initial PC == Reset_Ha - ndler - 10 00000000 ;* - Set the vector table entries w - ith the exceptions ISR address - 11 00000000 ;* - Configure the clock system - 12 00000000 ;* - Branches to __main in the C li - brary (which eventually - 13 00000000 ;* calls main()). - 14 00000000 ;* After Reset the Cortex-M3 proces - sor is in Thread mode, - 15 00000000 ;* priority is Privileged, and the - Stack is set to Main. - 16 00000000 ;******************************************************* - ************************* - 17 00000000 ;* - 18 00000000 ;*

    © COPYRIGHT(c) 2017 STMicroelectroni - cs

    - 19 00000000 ;* - 20 00000000 ;* Redistribution and use in source and binary forms, wi - th or without modification, - 21 00000000 ;* are permitted provided that the following conditions - are met: - 22 00000000 ;* 1. Redistributions of source code must retain the a - bove copyright notice, - 23 00000000 ;* this list of conditions and the following discla - imer. - 24 00000000 ;* 2. Redistributions in binary form must reproduce th - e above copyright notice, - 25 00000000 ;* this list of conditions and the following discla - imer in the documentation - 26 00000000 ;* and/or other materials provided with the distrib - ution. - 27 00000000 ;* 3. Neither the name of STMicroelectronics nor the n - ames of its contributors - 28 00000000 ;* may be used to endorse or promote products deriv - ed from this software - 29 00000000 ;* without specific prior written permission. - 30 00000000 ;* - 31 00000000 ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AN - D CONTRIBUTORS "AS IS" - 32 00000000 ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT - NOT LIMITED TO, THE - 33 00000000 ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - A PARTICULAR PURPOSE ARE - 34 00000000 ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - CONTRIBUTORS BE LIABLE - 35 00000000 ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPL - ARY, OR CONSEQUENTIAL - 36 00000000 ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT O - - - -ARM Macro Assembler Page 2 - - - F SUBSTITUTE GOODS OR - 37 00000000 ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER - 38 00000000 ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CON - TRACT, STRICT LIABILITY, - 39 00000000 ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING I - N ANY WAY OUT OF THE USE - 40 00000000 ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - OF SUCH DAMAGE. - 41 00000000 ; - 42 00000000 ;******************************************************* - ************************ - 43 00000000 - 44 00000000 ; Amount of memory (in bytes) allocated for Stack - 45 00000000 ; Tailor this value to your application needs - 46 00000000 ; Stack Configuration - 47 00000000 ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - 48 00000000 ; - 49 00000000 - 50 00000000 00001000 - Stack_Size - EQU 0x1000 - 51 00000000 - 52 00000000 AREA STACK, NOINIT, READWRITE, ALIGN -=3 - 53 00000000 Stack_Mem - SPACE Stack_Size - 54 00001000 __initial_sp - 55 00001000 - 56 00001000 ; Heap Configuration - 57 00001000 ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - 58 00001000 ; - 59 00001000 - 60 00001000 0000C000 - Heap_Size - EQU 0xC000 - 61 00001000 - 62 00001000 AREA HEAP, NOINIT, READWRITE, ALIGN= -3 - 63 00000000 __heap_base - 64 00000000 Heap_Mem - SPACE Heap_Size - 65 0000C000 __heap_limit - 66 0000C000 - 67 0000C000 PRESERVE8 - 68 0000C000 THUMB - 69 0000C000 - 70 0000C000 - 71 0000C000 ; Vector Table Mapped to Address 0 at Reset - 72 0000C000 AREA RESET, DATA, READONLY - 73 00000000 EXPORT __Vectors - 74 00000000 EXPORT __Vectors_End - 75 00000000 EXPORT __Vectors_Size - 76 00000000 - 77 00000000 00000000 - __Vectors - DCD __initial_sp ; Top of Stack - 78 00000004 00000000 DCD Reset_Handler ; Reset Handler - 79 00000008 00000000 DCD NMI_Handler ; NMI Handler - - - -ARM Macro Assembler Page 3 - - - 80 0000000C 00000000 DCD HardFault_Handler ; Hard Fault - Handler - 81 00000010 00000000 DCD MemManage_Handler - ; MPU Fault Handler - - 82 00000014 00000000 DCD BusFault_Handler - ; Bus Fault Handler - - 83 00000018 00000000 DCD UsageFault_Handler ; Usage Faul - t Handler - 84 0000001C 00000000 DCD 0 ; Reserved - 85 00000020 00000000 DCD 0 ; Reserved - 86 00000024 00000000 DCD 0 ; Reserved - 87 00000028 00000000 DCD 0 ; Reserved - 88 0000002C 00000000 DCD SVC_Handler ; SVCall Handler - 89 00000030 00000000 DCD DebugMon_Handler ; Debug Monito - r Handler - 90 00000034 00000000 DCD 0 ; Reserved - 91 00000038 00000000 DCD PendSV_Handler ; PendSV Handler - - 92 0000003C 00000000 DCD SysTick_Handler - ; SysTick Handler - 93 00000040 - 94 00000040 ; External Interrupts - 95 00000040 00000000 DCD WWDG_IRQHandler - ; Window Watchdog - 96 00000044 00000000 DCD PVD_IRQHandler ; PVD through EX - TI Line detect - 97 00000048 00000000 DCD TAMPER_IRQHandler ; Tamper - 98 0000004C 00000000 DCD RTC_IRQHandler ; RTC - 99 00000050 00000000 DCD FLASH_IRQHandler ; Flash - 100 00000054 00000000 DCD RCC_IRQHandler ; RCC - 101 00000058 00000000 DCD EXTI0_IRQHandler ; EXTI Line 0 - 102 0000005C 00000000 DCD EXTI1_IRQHandler ; EXTI Line 1 - 103 00000060 00000000 DCD EXTI2_IRQHandler ; EXTI Line 2 - 104 00000064 00000000 DCD EXTI3_IRQHandler ; EXTI Line 3 - 105 00000068 00000000 DCD EXTI4_IRQHandler ; EXTI Line 4 - 106 0000006C 00000000 DCD DMA1_Channel1_IRQHandler - ; DMA1 Channel 1 - 107 00000070 00000000 DCD DMA1_Channel2_IRQHandler - ; DMA1 Channel 2 - 108 00000074 00000000 DCD DMA1_Channel3_IRQHandler - ; DMA1 Channel 3 - 109 00000078 00000000 DCD DMA1_Channel4_IRQHandler - ; DMA1 Channel 4 - 110 0000007C 00000000 DCD DMA1_Channel5_IRQHandler - ; DMA1 Channel 5 - 111 00000080 00000000 DCD DMA1_Channel6_IRQHandler - ; DMA1 Channel 6 - 112 00000084 00000000 DCD DMA1_Channel7_IRQHandler - ; DMA1 Channel 7 - 113 00000088 00000000 DCD ADC1_2_IRQHandler ; ADC1 & ADC2 - - 114 0000008C 00000000 DCD USB_HP_CAN1_TX_IRQHandler ; USB - High Priority or C - AN1 TX - 115 00000090 00000000 DCD USB_LP_CAN1_RX0_IRQHandler ; US - B Low Priority or - CAN1 RX0 - - - -ARM Macro Assembler Page 4 - - - 116 00000094 00000000 DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - 117 00000098 00000000 DCD CAN1_SCE_IRQHandler ; CAN1 SCE - 118 0000009C 00000000 DCD EXTI9_5_IRQHandler - ; EXTI Line 9..5 - 119 000000A0 00000000 DCD TIM1_BRK_IRQHandler - ; TIM1 Break - 120 000000A4 00000000 DCD TIM1_UP_IRQHandler - ; TIM1 Update - 121 000000A8 00000000 DCD TIM1_TRG_COM_IRQHandler ; TIM1 - Trigger and Commuta - tion - 122 000000AC 00000000 DCD TIM1_CC_IRQHandler ; TIM1 Captu - re Compare - 123 000000B0 00000000 DCD TIM2_IRQHandler ; TIM2 - 124 000000B4 00000000 DCD TIM3_IRQHandler ; TIM3 - 125 000000B8 00000000 DCD TIM4_IRQHandler ; TIM4 - 126 000000BC 00000000 DCD I2C1_EV_IRQHandler ; I2C1 Event - - 127 000000C0 00000000 DCD I2C1_ER_IRQHandler ; I2C1 Error - - 128 000000C4 00000000 DCD I2C2_EV_IRQHandler ; I2C2 Event - - 129 000000C8 00000000 DCD I2C2_ER_IRQHandler ; I2C2 Error - - 130 000000CC 00000000 DCD SPI1_IRQHandler ; SPI1 - 131 000000D0 00000000 DCD SPI2_IRQHandler ; SPI2 - 132 000000D4 00000000 DCD USART1_IRQHandler ; USART1 - 133 000000D8 00000000 DCD USART2_IRQHandler ; USART2 - 134 000000DC 00000000 DCD USART3_IRQHandler ; USART3 - 135 000000E0 00000000 DCD EXTI15_10_IRQHandler - ; EXTI Line 15..10 - 136 000000E4 00000000 DCD RTC_Alarm_IRQHandler ; RTC Alar - m through EXTI Line - - 137 000000E8 00000000 DCD USBWakeUp_IRQHandler ; USB Wake - up from suspend - 138 000000EC 00000000 DCD TIM8_BRK_IRQHandler - ; TIM8 Break - 139 000000F0 00000000 DCD TIM8_UP_IRQHandler - ; TIM8 Update - 140 000000F4 00000000 DCD TIM8_TRG_COM_IRQHandler ; TIM8 - Trigger and Commuta - tion - 141 000000F8 00000000 DCD TIM8_CC_IRQHandler ; TIM8 Captu - re Compare - 142 000000FC 00000000 DCD ADC3_IRQHandler ; ADC3 - 143 00000100 00000000 DCD FSMC_IRQHandler ; FSMC - 144 00000104 00000000 DCD SDIO_IRQHandler ; SDIO - 145 00000108 00000000 DCD TIM5_IRQHandler ; TIM5 - 146 0000010C 00000000 DCD SPI3_IRQHandler ; SPI3 - 147 00000110 00000000 DCD UART4_IRQHandler ; UART4 - 148 00000114 00000000 DCD UART5_IRQHandler ; UART5 - 149 00000118 00000000 DCD TIM6_IRQHandler ; TIM6 - 150 0000011C 00000000 DCD TIM7_IRQHandler ; TIM7 - 151 00000120 00000000 DCD DMA2_Channel1_IRQHandler - ; DMA2 Channel1 - 152 00000124 00000000 DCD DMA2_Channel2_IRQHandler - ; DMA2 Channel2 - 153 00000128 00000000 DCD DMA2_Channel3_IRQHandler - - - -ARM Macro Assembler Page 5 - - - ; DMA2 Channel3 - 154 0000012C 00000000 DCD DMA2_Channel4_5_IRQHandler ; DM - A2 Channel4 & Chann - el5 - 155 00000130 __Vectors_End - 156 00000130 - 157 00000130 00000130 - __Vectors_Size - EQU __Vectors_End - __Vectors - 158 00000130 - 159 00000130 AREA |.text|, CODE, READONLY - 160 00000000 - 161 00000000 ; Reset handler - 162 00000000 Reset_Handler - PROC - 163 00000000 EXPORT Reset_Handler [WEAK -] - 164 00000000 IMPORT __main - 165 00000000 IMPORT SystemInit - 166 00000000 4806 LDR R0, =SystemInit - 167 00000002 4780 BLX R0 - 168 00000004 4806 LDR R0, =__main - 169 00000006 4700 BX R0 - 170 00000008 ENDP - 171 00000008 - 172 00000008 ; Dummy Exception Handlers (infinite loops which can be - modified) - 173 00000008 - 174 00000008 NMI_Handler - PROC - 175 00000008 EXPORT NMI_Handler [WEA -K] - 176 00000008 E7FE B . - 177 0000000A ENDP - 179 0000000A HardFault_Handler - PROC - 180 0000000A EXPORT HardFault_Handler [WEA -K] - 181 0000000A E7FE B . - 182 0000000C ENDP - 184 0000000C MemManage_Handler - PROC - 185 0000000C EXPORT MemManage_Handler [WEA -K] - 186 0000000C E7FE B . - 187 0000000E ENDP - 189 0000000E BusFault_Handler - PROC - 190 0000000E EXPORT BusFault_Handler [WEA -K] - 191 0000000E E7FE B . - 192 00000010 ENDP - 194 00000010 UsageFault_Handler - PROC - 195 00000010 EXPORT UsageFault_Handler [WEA -K] - 196 00000010 E7FE B . - 197 00000012 ENDP - 198 00000012 SVC_Handler - - - -ARM Macro Assembler Page 6 - - - PROC - 199 00000012 EXPORT SVC_Handler [WEA -K] - 200 00000012 E7FE B . - 201 00000014 ENDP - 203 00000014 DebugMon_Handler - PROC - 204 00000014 EXPORT DebugMon_Handler [WEA -K] - 205 00000014 E7FE B . - 206 00000016 ENDP - 207 00000016 PendSV_Handler - PROC - 208 00000016 EXPORT PendSV_Handler [WEA -K] - 209 00000016 E7FE B . - 210 00000018 ENDP - 211 00000018 SysTick_Handler - PROC - 212 00000018 EXPORT SysTick_Handler [WEA -K] - 213 00000018 E7FE B . - 214 0000001A ENDP - 215 0000001A - 216 0000001A Default_Handler - PROC - 217 0000001A - 218 0000001A EXPORT WWDG_IRQHandler [WEA -K] - 219 0000001A EXPORT PVD_IRQHandler [WEA -K] - 220 0000001A EXPORT TAMPER_IRQHandler [WEA -K] - 221 0000001A EXPORT RTC_IRQHandler [WEA -K] - 222 0000001A EXPORT FLASH_IRQHandler [WEA -K] - 223 0000001A EXPORT RCC_IRQHandler [WEA -K] - 224 0000001A EXPORT EXTI0_IRQHandler [WEA -K] - 225 0000001A EXPORT EXTI1_IRQHandler [WEA -K] - 226 0000001A EXPORT EXTI2_IRQHandler [WEA -K] - 227 0000001A EXPORT EXTI3_IRQHandler [WEA -K] - 228 0000001A EXPORT EXTI4_IRQHandler [WEA -K] - 229 0000001A EXPORT DMA1_Channel1_IRQHandler [WEA -K] - 230 0000001A EXPORT DMA1_Channel2_IRQHandler [WEA -K] - 231 0000001A EXPORT DMA1_Channel3_IRQHandler [WEA -K] - 232 0000001A EXPORT DMA1_Channel4_IRQHandler [WEA -K] - 233 0000001A EXPORT DMA1_Channel5_IRQHandler [WEA -K] - - - -ARM Macro Assembler Page 7 - - - 234 0000001A EXPORT DMA1_Channel6_IRQHandler [WEA -K] - 235 0000001A EXPORT DMA1_Channel7_IRQHandler [WEA -K] - 236 0000001A EXPORT ADC1_2_IRQHandler [WEA -K] - 237 0000001A EXPORT USB_HP_CAN1_TX_IRQHandler [WEA -K] - 238 0000001A EXPORT USB_LP_CAN1_RX0_IRQHandler [WEA -K] - 239 0000001A EXPORT CAN1_RX1_IRQHandler [WEA -K] - 240 0000001A EXPORT CAN1_SCE_IRQHandler [WEA -K] - 241 0000001A EXPORT EXTI9_5_IRQHandler [WEA -K] - 242 0000001A EXPORT TIM1_BRK_IRQHandler [WEA -K] - 243 0000001A EXPORT TIM1_UP_IRQHandler [WEA -K] - 244 0000001A EXPORT TIM1_TRG_COM_IRQHandler [WEA -K] - 245 0000001A EXPORT TIM1_CC_IRQHandler [WEA -K] - 246 0000001A EXPORT TIM2_IRQHandler [WEA -K] - 247 0000001A EXPORT TIM3_IRQHandler [WEA -K] - 248 0000001A EXPORT TIM4_IRQHandler [WEA -K] - 249 0000001A EXPORT I2C1_EV_IRQHandler [WEA -K] - 250 0000001A EXPORT I2C1_ER_IRQHandler [WEA -K] - 251 0000001A EXPORT I2C2_EV_IRQHandler [WEA -K] - 252 0000001A EXPORT I2C2_ER_IRQHandler [WEA -K] - 253 0000001A EXPORT SPI1_IRQHandler [WEA -K] - 254 0000001A EXPORT SPI2_IRQHandler [WEA -K] - 255 0000001A EXPORT USART1_IRQHandler [WEA -K] - 256 0000001A EXPORT USART2_IRQHandler [WEA -K] - 257 0000001A EXPORT USART3_IRQHandler [WEA -K] - 258 0000001A EXPORT EXTI15_10_IRQHandler [WEA -K] - 259 0000001A EXPORT RTC_Alarm_IRQHandler [WE -AK] - 260 0000001A EXPORT USBWakeUp_IRQHandler [WEA -K] - 261 0000001A EXPORT TIM8_BRK_IRQHandler [WEA -K] - 262 0000001A EXPORT TIM8_UP_IRQHandler [WEA -K] - 263 0000001A EXPORT TIM8_TRG_COM_IRQHandler [WEA - - - -ARM Macro Assembler Page 8 - - -K] - 264 0000001A EXPORT TIM8_CC_IRQHandler [WEA -K] - 265 0000001A EXPORT ADC3_IRQHandler [WEA -K] - 266 0000001A EXPORT FSMC_IRQHandler [WEA -K] - 267 0000001A EXPORT SDIO_IRQHandler [WEA -K] - 268 0000001A EXPORT TIM5_IRQHandler [WEA -K] - 269 0000001A EXPORT SPI3_IRQHandler [WEA -K] - 270 0000001A EXPORT UART4_IRQHandler [WEA -K] - 271 0000001A EXPORT UART5_IRQHandler [WEA -K] - 272 0000001A EXPORT TIM6_IRQHandler [WEA -K] - 273 0000001A EXPORT TIM7_IRQHandler [WEA -K] - 274 0000001A EXPORT DMA2_Channel1_IRQHandler [WEA -K] - 275 0000001A EXPORT DMA2_Channel2_IRQHandler [WEA -K] - 276 0000001A EXPORT DMA2_Channel3_IRQHandler [WEA -K] - 277 0000001A EXPORT DMA2_Channel4_5_IRQHandler [WEA -K] - 278 0000001A - 279 0000001A WWDG_IRQHandler - 280 0000001A PVD_IRQHandler - 281 0000001A TAMPER_IRQHandler - 282 0000001A RTC_IRQHandler - 283 0000001A FLASH_IRQHandler - 284 0000001A RCC_IRQHandler - 285 0000001A EXTI0_IRQHandler - 286 0000001A EXTI1_IRQHandler - 287 0000001A EXTI2_IRQHandler - 288 0000001A EXTI3_IRQHandler - 289 0000001A EXTI4_IRQHandler - 290 0000001A DMA1_Channel1_IRQHandler - 291 0000001A DMA1_Channel2_IRQHandler - 292 0000001A DMA1_Channel3_IRQHandler - 293 0000001A DMA1_Channel4_IRQHandler - 294 0000001A DMA1_Channel5_IRQHandler - 295 0000001A DMA1_Channel6_IRQHandler - 296 0000001A DMA1_Channel7_IRQHandler - 297 0000001A ADC1_2_IRQHandler - 298 0000001A USB_HP_CAN1_TX_IRQHandler - 299 0000001A USB_LP_CAN1_RX0_IRQHandler - 300 0000001A CAN1_RX1_IRQHandler - 301 0000001A CAN1_SCE_IRQHandler - 302 0000001A EXTI9_5_IRQHandler - 303 0000001A TIM1_BRK_IRQHandler - 304 0000001A TIM1_UP_IRQHandler - 305 0000001A TIM1_TRG_COM_IRQHandler - 306 0000001A TIM1_CC_IRQHandler - 307 0000001A TIM2_IRQHandler - - - -ARM Macro Assembler Page 9 - - - 308 0000001A TIM3_IRQHandler - 309 0000001A TIM4_IRQHandler - 310 0000001A I2C1_EV_IRQHandler - 311 0000001A I2C1_ER_IRQHandler - 312 0000001A I2C2_EV_IRQHandler - 313 0000001A I2C2_ER_IRQHandler - 314 0000001A SPI1_IRQHandler - 315 0000001A SPI2_IRQHandler - 316 0000001A USART1_IRQHandler - 317 0000001A USART2_IRQHandler - 318 0000001A USART3_IRQHandler - 319 0000001A EXTI15_10_IRQHandler - 320 0000001A RTC_Alarm_IRQHandler - 321 0000001A USBWakeUp_IRQHandler - 322 0000001A TIM8_BRK_IRQHandler - 323 0000001A TIM8_UP_IRQHandler - 324 0000001A TIM8_TRG_COM_IRQHandler - 325 0000001A TIM8_CC_IRQHandler - 326 0000001A ADC3_IRQHandler - 327 0000001A FSMC_IRQHandler - 328 0000001A SDIO_IRQHandler - 329 0000001A TIM5_IRQHandler - 330 0000001A SPI3_IRQHandler - 331 0000001A UART4_IRQHandler - 332 0000001A UART5_IRQHandler - 333 0000001A TIM6_IRQHandler - 334 0000001A TIM7_IRQHandler - 335 0000001A DMA2_Channel1_IRQHandler - 336 0000001A DMA2_Channel2_IRQHandler - 337 0000001A DMA2_Channel3_IRQHandler - 338 0000001A DMA2_Channel4_5_IRQHandler - 339 0000001A E7FE B . - 340 0000001C - 341 0000001C ENDP - 342 0000001C - 343 0000001C ALIGN - 344 0000001C - 345 0000001C ;******************************************************* - ************************ - 346 0000001C ; User Stack and Heap initialization - 347 0000001C ;******************************************************* - ************************ - 348 0000001C IF :DEF:__MICROLIB - 349 0000001C - 350 0000001C EXPORT __initial_sp - 351 0000001C EXPORT __heap_base - 352 0000001C EXPORT __heap_limit - 353 0000001C - 354 0000001C ELSE - 369 ENDIF - 370 0000001C - 371 0000001C END - 00000000 - 00000000 -Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw -ork --depend=epd-demo\startup_stm32f103xe.d -oepd-demo\startup_stm32f103xe.o -I -.\RTE\_epd-demo -ID:\KEIL\azwz\ARM\PACK\ARM\CMSIS\5.9.0\CMSIS\Core\Include -ID: -\KEIL\azwz\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include --predefine="__MICR -OLIB SETA 1" --predefine="__UVISION_VERSION SETA 526" --predefine="_RTE_ SETA 1 - - - -ARM Macro Assembler Page 10 - - -" --predefine="STM32F10X_HD SETA 1" --list=startup_stm32f103xe.lst startup_stm3 -2f103xe.s - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Relocatable symbols - -STACK 00000000 - -Symbol: STACK - Definitions - At line 52 in file startup_stm32f103xe.s - Uses - None -Comment: STACK unused -Stack_Mem 00000000 - -Symbol: Stack_Mem - Definitions - At line 53 in file startup_stm32f103xe.s - Uses - None -Comment: Stack_Mem unused -__initial_sp 00001000 - -Symbol: __initial_sp - Definitions - At line 54 in file startup_stm32f103xe.s - Uses - At line 77 in file startup_stm32f103xe.s - At line 350 in file startup_stm32f103xe.s - -3 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Relocatable symbols - -HEAP 00000000 - -Symbol: HEAP - Definitions - At line 62 in file startup_stm32f103xe.s - Uses - None -Comment: HEAP unused -Heap_Mem 00000000 - -Symbol: Heap_Mem - Definitions - At line 64 in file startup_stm32f103xe.s - Uses - None -Comment: Heap_Mem unused -__heap_base 00000000 - -Symbol: __heap_base - Definitions - At line 63 in file startup_stm32f103xe.s - Uses - At line 351 in file startup_stm32f103xe.s -Comment: __heap_base used once -__heap_limit 0000C000 - -Symbol: __heap_limit - Definitions - At line 65 in file startup_stm32f103xe.s - Uses - At line 352 in file startup_stm32f103xe.s -Comment: __heap_limit used once -4 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Relocatable symbols - -RESET 00000000 - -Symbol: RESET - Definitions - At line 72 in file startup_stm32f103xe.s - Uses - None -Comment: RESET unused -__Vectors 00000000 - -Symbol: __Vectors - Definitions - At line 77 in file startup_stm32f103xe.s - Uses - At line 73 in file startup_stm32f103xe.s - At line 157 in file startup_stm32f103xe.s - -__Vectors_End 00000130 - -Symbol: __Vectors_End - Definitions - At line 155 in file startup_stm32f103xe.s - Uses - At line 74 in file startup_stm32f103xe.s - At line 157 in file startup_stm32f103xe.s - -3 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Relocatable symbols - -.text 00000000 - -Symbol: .text - Definitions - At line 159 in file startup_stm32f103xe.s - Uses - None -Comment: .text unused -ADC1_2_IRQHandler 0000001A - -Symbol: ADC1_2_IRQHandler - Definitions - At line 297 in file startup_stm32f103xe.s - Uses - At line 113 in file startup_stm32f103xe.s - At line 236 in file startup_stm32f103xe.s - -ADC3_IRQHandler 0000001A - -Symbol: ADC3_IRQHandler - Definitions - At line 326 in file startup_stm32f103xe.s - Uses - At line 142 in file startup_stm32f103xe.s - At line 265 in file startup_stm32f103xe.s - -BusFault_Handler 0000000E - -Symbol: BusFault_Handler - Definitions - At line 189 in file startup_stm32f103xe.s - Uses - At line 82 in file startup_stm32f103xe.s - At line 190 in file startup_stm32f103xe.s - -CAN1_RX1_IRQHandler 0000001A - -Symbol: CAN1_RX1_IRQHandler - Definitions - At line 300 in file startup_stm32f103xe.s - Uses - At line 116 in file startup_stm32f103xe.s - At line 239 in file startup_stm32f103xe.s - -CAN1_SCE_IRQHandler 0000001A - -Symbol: CAN1_SCE_IRQHandler - Definitions - At line 301 in file startup_stm32f103xe.s - Uses - At line 117 in file startup_stm32f103xe.s - At line 240 in file startup_stm32f103xe.s - -DMA1_Channel1_IRQHandler 0000001A - -Symbol: DMA1_Channel1_IRQHandler - Definitions - At line 290 in file startup_stm32f103xe.s - Uses - - - -ARM Macro Assembler Page 2 Alphabetic symbol ordering -Relocatable symbols - - At line 106 in file startup_stm32f103xe.s - At line 229 in file startup_stm32f103xe.s - -DMA1_Channel2_IRQHandler 0000001A - -Symbol: DMA1_Channel2_IRQHandler - Definitions - At line 291 in file startup_stm32f103xe.s - Uses - At line 107 in file startup_stm32f103xe.s - At line 230 in file startup_stm32f103xe.s - -DMA1_Channel3_IRQHandler 0000001A - -Symbol: DMA1_Channel3_IRQHandler - Definitions - At line 292 in file startup_stm32f103xe.s - Uses - At line 108 in file startup_stm32f103xe.s - At line 231 in file startup_stm32f103xe.s - -DMA1_Channel4_IRQHandler 0000001A - -Symbol: DMA1_Channel4_IRQHandler - Definitions - At line 293 in file startup_stm32f103xe.s - Uses - At line 109 in file startup_stm32f103xe.s - At line 232 in file startup_stm32f103xe.s - -DMA1_Channel5_IRQHandler 0000001A - -Symbol: DMA1_Channel5_IRQHandler - Definitions - At line 294 in file startup_stm32f103xe.s - Uses - At line 110 in file startup_stm32f103xe.s - At line 233 in file startup_stm32f103xe.s - -DMA1_Channel6_IRQHandler 0000001A - -Symbol: DMA1_Channel6_IRQHandler - Definitions - At line 295 in file startup_stm32f103xe.s - Uses - At line 111 in file startup_stm32f103xe.s - At line 234 in file startup_stm32f103xe.s - -DMA1_Channel7_IRQHandler 0000001A - -Symbol: DMA1_Channel7_IRQHandler - Definitions - At line 296 in file startup_stm32f103xe.s - Uses - At line 112 in file startup_stm32f103xe.s - At line 235 in file startup_stm32f103xe.s - -DMA2_Channel1_IRQHandler 0000001A - - - - -ARM Macro Assembler Page 3 Alphabetic symbol ordering -Relocatable symbols - -Symbol: DMA2_Channel1_IRQHandler - Definitions - At line 335 in file startup_stm32f103xe.s - Uses - At line 151 in file startup_stm32f103xe.s - At line 274 in file startup_stm32f103xe.s - -DMA2_Channel2_IRQHandler 0000001A - -Symbol: DMA2_Channel2_IRQHandler - Definitions - At line 336 in file startup_stm32f103xe.s - Uses - At line 152 in file startup_stm32f103xe.s - At line 275 in file startup_stm32f103xe.s - -DMA2_Channel3_IRQHandler 0000001A - -Symbol: DMA2_Channel3_IRQHandler - Definitions - At line 337 in file startup_stm32f103xe.s - Uses - At line 153 in file startup_stm32f103xe.s - At line 276 in file startup_stm32f103xe.s - -DMA2_Channel4_5_IRQHandler 0000001A - -Symbol: DMA2_Channel4_5_IRQHandler - Definitions - At line 338 in file startup_stm32f103xe.s - Uses - At line 154 in file startup_stm32f103xe.s - At line 277 in file startup_stm32f103xe.s - -DebugMon_Handler 00000014 - -Symbol: DebugMon_Handler - Definitions - At line 203 in file startup_stm32f103xe.s - Uses - At line 89 in file startup_stm32f103xe.s - At line 204 in file startup_stm32f103xe.s - -Default_Handler 0000001A - -Symbol: Default_Handler - Definitions - At line 216 in file startup_stm32f103xe.s - Uses - None -Comment: Default_Handler unused -EXTI0_IRQHandler 0000001A - -Symbol: EXTI0_IRQHandler - Definitions - At line 285 in file startup_stm32f103xe.s - Uses - At line 101 in file startup_stm32f103xe.s - At line 224 in file startup_stm32f103xe.s - - - -ARM Macro Assembler Page 4 Alphabetic symbol ordering -Relocatable symbols - - -EXTI15_10_IRQHandler 0000001A - -Symbol: EXTI15_10_IRQHandler - Definitions - At line 319 in file startup_stm32f103xe.s - Uses - At line 135 in file startup_stm32f103xe.s - At line 258 in file startup_stm32f103xe.s - -EXTI1_IRQHandler 0000001A - -Symbol: EXTI1_IRQHandler - Definitions - At line 286 in file startup_stm32f103xe.s - Uses - At line 102 in file startup_stm32f103xe.s - At line 225 in file startup_stm32f103xe.s - -EXTI2_IRQHandler 0000001A - -Symbol: EXTI2_IRQHandler - Definitions - At line 287 in file startup_stm32f103xe.s - Uses - At line 103 in file startup_stm32f103xe.s - At line 226 in file startup_stm32f103xe.s - -EXTI3_IRQHandler 0000001A - -Symbol: EXTI3_IRQHandler - Definitions - At line 288 in file startup_stm32f103xe.s - Uses - At line 104 in file startup_stm32f103xe.s - At line 227 in file startup_stm32f103xe.s - -EXTI4_IRQHandler 0000001A - -Symbol: EXTI4_IRQHandler - Definitions - At line 289 in file startup_stm32f103xe.s - Uses - At line 105 in file startup_stm32f103xe.s - At line 228 in file startup_stm32f103xe.s - -EXTI9_5_IRQHandler 0000001A - -Symbol: EXTI9_5_IRQHandler - Definitions - At line 302 in file startup_stm32f103xe.s - Uses - At line 118 in file startup_stm32f103xe.s - At line 241 in file startup_stm32f103xe.s - -FLASH_IRQHandler 0000001A - -Symbol: FLASH_IRQHandler - Definitions - - - -ARM Macro Assembler Page 5 Alphabetic symbol ordering -Relocatable symbols - - At line 283 in file startup_stm32f103xe.s - Uses - At line 99 in file startup_stm32f103xe.s - At line 222 in file startup_stm32f103xe.s - -FSMC_IRQHandler 0000001A - -Symbol: FSMC_IRQHandler - Definitions - At line 327 in file startup_stm32f103xe.s - Uses - At line 143 in file startup_stm32f103xe.s - At line 266 in file startup_stm32f103xe.s - -HardFault_Handler 0000000A - -Symbol: HardFault_Handler - Definitions - At line 179 in file startup_stm32f103xe.s - Uses - At line 80 in file startup_stm32f103xe.s - At line 180 in file startup_stm32f103xe.s - -I2C1_ER_IRQHandler 0000001A - -Symbol: I2C1_ER_IRQHandler - Definitions - At line 311 in file startup_stm32f103xe.s - Uses - At line 127 in file startup_stm32f103xe.s - At line 250 in file startup_stm32f103xe.s - -I2C1_EV_IRQHandler 0000001A - -Symbol: I2C1_EV_IRQHandler - Definitions - At line 310 in file startup_stm32f103xe.s - Uses - At line 126 in file startup_stm32f103xe.s - At line 249 in file startup_stm32f103xe.s - -I2C2_ER_IRQHandler 0000001A - -Symbol: I2C2_ER_IRQHandler - Definitions - At line 313 in file startup_stm32f103xe.s - Uses - At line 129 in file startup_stm32f103xe.s - At line 252 in file startup_stm32f103xe.s - -I2C2_EV_IRQHandler 0000001A - -Symbol: I2C2_EV_IRQHandler - Definitions - At line 312 in file startup_stm32f103xe.s - Uses - At line 128 in file startup_stm32f103xe.s - At line 251 in file startup_stm32f103xe.s - - - - -ARM Macro Assembler Page 6 Alphabetic symbol ordering -Relocatable symbols - -MemManage_Handler 0000000C - -Symbol: MemManage_Handler - Definitions - At line 184 in file startup_stm32f103xe.s - Uses - At line 81 in file startup_stm32f103xe.s - At line 185 in file startup_stm32f103xe.s - -NMI_Handler 00000008 - -Symbol: NMI_Handler - Definitions - At line 174 in file startup_stm32f103xe.s - Uses - At line 79 in file startup_stm32f103xe.s - At line 175 in file startup_stm32f103xe.s - -PVD_IRQHandler 0000001A - -Symbol: PVD_IRQHandler - Definitions - At line 280 in file startup_stm32f103xe.s - Uses - At line 96 in file startup_stm32f103xe.s - At line 219 in file startup_stm32f103xe.s - -PendSV_Handler 00000016 - -Symbol: PendSV_Handler - Definitions - At line 207 in file startup_stm32f103xe.s - Uses - At line 91 in file startup_stm32f103xe.s - At line 208 in file startup_stm32f103xe.s - -RCC_IRQHandler 0000001A - -Symbol: RCC_IRQHandler - Definitions - At line 284 in file startup_stm32f103xe.s - Uses - At line 100 in file startup_stm32f103xe.s - At line 223 in file startup_stm32f103xe.s - -RTC_Alarm_IRQHandler 0000001A - -Symbol: RTC_Alarm_IRQHandler - Definitions - At line 320 in file startup_stm32f103xe.s - Uses - At line 136 in file startup_stm32f103xe.s - At line 259 in file startup_stm32f103xe.s - -RTC_IRQHandler 0000001A - -Symbol: RTC_IRQHandler - Definitions - At line 282 in file startup_stm32f103xe.s - - - -ARM Macro Assembler Page 7 Alphabetic symbol ordering -Relocatable symbols - - Uses - At line 98 in file startup_stm32f103xe.s - At line 221 in file startup_stm32f103xe.s - -Reset_Handler 00000000 - -Symbol: Reset_Handler - Definitions - At line 162 in file startup_stm32f103xe.s - Uses - At line 78 in file startup_stm32f103xe.s - At line 163 in file startup_stm32f103xe.s - -SDIO_IRQHandler 0000001A - -Symbol: SDIO_IRQHandler - Definitions - At line 328 in file startup_stm32f103xe.s - Uses - At line 144 in file startup_stm32f103xe.s - At line 267 in file startup_stm32f103xe.s - -SPI1_IRQHandler 0000001A - -Symbol: SPI1_IRQHandler - Definitions - At line 314 in file startup_stm32f103xe.s - Uses - At line 130 in file startup_stm32f103xe.s - At line 253 in file startup_stm32f103xe.s - -SPI2_IRQHandler 0000001A - -Symbol: SPI2_IRQHandler - Definitions - At line 315 in file startup_stm32f103xe.s - Uses - At line 131 in file startup_stm32f103xe.s - At line 254 in file startup_stm32f103xe.s - -SPI3_IRQHandler 0000001A - -Symbol: SPI3_IRQHandler - Definitions - At line 330 in file startup_stm32f103xe.s - Uses - At line 146 in file startup_stm32f103xe.s - At line 269 in file startup_stm32f103xe.s - -SVC_Handler 00000012 - -Symbol: SVC_Handler - Definitions - At line 198 in file startup_stm32f103xe.s - Uses - At line 88 in file startup_stm32f103xe.s - At line 199 in file startup_stm32f103xe.s - -SysTick_Handler 00000018 - - - -ARM Macro Assembler Page 8 Alphabetic symbol ordering -Relocatable symbols - - -Symbol: SysTick_Handler - Definitions - At line 211 in file startup_stm32f103xe.s - Uses - At line 92 in file startup_stm32f103xe.s - At line 212 in file startup_stm32f103xe.s - -TAMPER_IRQHandler 0000001A - -Symbol: TAMPER_IRQHandler - Definitions - At line 281 in file startup_stm32f103xe.s - Uses - At line 97 in file startup_stm32f103xe.s - At line 220 in file startup_stm32f103xe.s - -TIM1_BRK_IRQHandler 0000001A - -Symbol: TIM1_BRK_IRQHandler - Definitions - At line 303 in file startup_stm32f103xe.s - Uses - At line 119 in file startup_stm32f103xe.s - At line 242 in file startup_stm32f103xe.s - -TIM1_CC_IRQHandler 0000001A - -Symbol: TIM1_CC_IRQHandler - Definitions - At line 306 in file startup_stm32f103xe.s - Uses - At line 122 in file startup_stm32f103xe.s - At line 245 in file startup_stm32f103xe.s - -TIM1_TRG_COM_IRQHandler 0000001A - -Symbol: TIM1_TRG_COM_IRQHandler - Definitions - At line 305 in file startup_stm32f103xe.s - Uses - At line 121 in file startup_stm32f103xe.s - At line 244 in file startup_stm32f103xe.s - -TIM1_UP_IRQHandler 0000001A - -Symbol: TIM1_UP_IRQHandler - Definitions - At line 304 in file startup_stm32f103xe.s - Uses - At line 120 in file startup_stm32f103xe.s - At line 243 in file startup_stm32f103xe.s - -TIM2_IRQHandler 0000001A - -Symbol: TIM2_IRQHandler - Definitions - At line 307 in file startup_stm32f103xe.s - Uses - - - -ARM Macro Assembler Page 9 Alphabetic symbol ordering -Relocatable symbols - - At line 123 in file startup_stm32f103xe.s - At line 246 in file startup_stm32f103xe.s - -TIM3_IRQHandler 0000001A - -Symbol: TIM3_IRQHandler - Definitions - At line 308 in file startup_stm32f103xe.s - Uses - At line 124 in file startup_stm32f103xe.s - At line 247 in file startup_stm32f103xe.s - -TIM4_IRQHandler 0000001A - -Symbol: TIM4_IRQHandler - Definitions - At line 309 in file startup_stm32f103xe.s - Uses - At line 125 in file startup_stm32f103xe.s - At line 248 in file startup_stm32f103xe.s - -TIM5_IRQHandler 0000001A - -Symbol: TIM5_IRQHandler - Definitions - At line 329 in file startup_stm32f103xe.s - Uses - At line 145 in file startup_stm32f103xe.s - At line 268 in file startup_stm32f103xe.s - -TIM6_IRQHandler 0000001A - -Symbol: TIM6_IRQHandler - Definitions - At line 333 in file startup_stm32f103xe.s - Uses - At line 149 in file startup_stm32f103xe.s - At line 272 in file startup_stm32f103xe.s - -TIM7_IRQHandler 0000001A - -Symbol: TIM7_IRQHandler - Definitions - At line 334 in file startup_stm32f103xe.s - Uses - At line 150 in file startup_stm32f103xe.s - At line 273 in file startup_stm32f103xe.s - -TIM8_BRK_IRQHandler 0000001A - -Symbol: TIM8_BRK_IRQHandler - Definitions - At line 322 in file startup_stm32f103xe.s - Uses - At line 138 in file startup_stm32f103xe.s - At line 261 in file startup_stm32f103xe.s - -TIM8_CC_IRQHandler 0000001A - - - - -ARM Macro Assembler Page 10 Alphabetic symbol ordering -Relocatable symbols - -Symbol: TIM8_CC_IRQHandler - Definitions - At line 325 in file startup_stm32f103xe.s - Uses - At line 141 in file startup_stm32f103xe.s - At line 264 in file startup_stm32f103xe.s - -TIM8_TRG_COM_IRQHandler 0000001A - -Symbol: TIM8_TRG_COM_IRQHandler - Definitions - At line 324 in file startup_stm32f103xe.s - Uses - At line 140 in file startup_stm32f103xe.s - At line 263 in file startup_stm32f103xe.s - -TIM8_UP_IRQHandler 0000001A - -Symbol: TIM8_UP_IRQHandler - Definitions - At line 323 in file startup_stm32f103xe.s - Uses - At line 139 in file startup_stm32f103xe.s - At line 262 in file startup_stm32f103xe.s - -UART4_IRQHandler 0000001A - -Symbol: UART4_IRQHandler - Definitions - At line 331 in file startup_stm32f103xe.s - Uses - At line 147 in file startup_stm32f103xe.s - At line 270 in file startup_stm32f103xe.s - -UART5_IRQHandler 0000001A - -Symbol: UART5_IRQHandler - Definitions - At line 332 in file startup_stm32f103xe.s - Uses - At line 148 in file startup_stm32f103xe.s - At line 271 in file startup_stm32f103xe.s - -USART1_IRQHandler 0000001A - -Symbol: USART1_IRQHandler - Definitions - At line 316 in file startup_stm32f103xe.s - Uses - At line 132 in file startup_stm32f103xe.s - At line 255 in file startup_stm32f103xe.s - -USART2_IRQHandler 0000001A - -Symbol: USART2_IRQHandler - Definitions - At line 317 in file startup_stm32f103xe.s - Uses - At line 133 in file startup_stm32f103xe.s - - - -ARM Macro Assembler Page 11 Alphabetic symbol ordering -Relocatable symbols - - At line 256 in file startup_stm32f103xe.s - -USART3_IRQHandler 0000001A - -Symbol: USART3_IRQHandler - Definitions - At line 318 in file startup_stm32f103xe.s - Uses - At line 134 in file startup_stm32f103xe.s - At line 257 in file startup_stm32f103xe.s - -USBWakeUp_IRQHandler 0000001A - -Symbol: USBWakeUp_IRQHandler - Definitions - At line 321 in file startup_stm32f103xe.s - Uses - At line 137 in file startup_stm32f103xe.s - At line 260 in file startup_stm32f103xe.s - -USB_HP_CAN1_TX_IRQHandler 0000001A - -Symbol: USB_HP_CAN1_TX_IRQHandler - Definitions - At line 298 in file startup_stm32f103xe.s - Uses - At line 114 in file startup_stm32f103xe.s - At line 237 in file startup_stm32f103xe.s - -USB_LP_CAN1_RX0_IRQHandler 0000001A - -Symbol: USB_LP_CAN1_RX0_IRQHandler - Definitions - At line 299 in file startup_stm32f103xe.s - Uses - At line 115 in file startup_stm32f103xe.s - At line 238 in file startup_stm32f103xe.s - -UsageFault_Handler 00000010 - -Symbol: UsageFault_Handler - Definitions - At line 194 in file startup_stm32f103xe.s - Uses - At line 83 in file startup_stm32f103xe.s - At line 195 in file startup_stm32f103xe.s - -WWDG_IRQHandler 0000001A - -Symbol: WWDG_IRQHandler - Definitions - At line 279 in file startup_stm32f103xe.s - Uses - At line 95 in file startup_stm32f103xe.s - At line 218 in file startup_stm32f103xe.s - -72 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Absolute symbols - -Heap_Size 0000C000 - -Symbol: Heap_Size - Definitions - At line 60 in file startup_stm32f103xe.s - Uses - At line 64 in file startup_stm32f103xe.s -Comment: Heap_Size used once -Stack_Size 00001000 - -Symbol: Stack_Size - Definitions - At line 50 in file startup_stm32f103xe.s - Uses - At line 53 in file startup_stm32f103xe.s -Comment: Stack_Size used once -__Vectors_Size 00000130 - -Symbol: __Vectors_Size - Definitions - At line 157 in file startup_stm32f103xe.s - Uses - At line 75 in file startup_stm32f103xe.s -Comment: __Vectors_Size used once -3 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -External symbols - -SystemInit 00000000 - -Symbol: SystemInit - Definitions - At line 165 in file startup_stm32f103xe.s - Uses - At line 166 in file startup_stm32f103xe.s -Comment: SystemInit used once -__main 00000000 - -Symbol: __main - Definitions - At line 164 in file startup_stm32f103xe.s - Uses - At line 168 in file startup_stm32f103xe.s -Comment: __main used once -2 symbols -423 symbols in table diff --git a/STM32/STM32-F103ZET6/Src/main.c b/STM32/STM32-F103ZET6/Src/main.c index 3d4c6ac..e62eb64 100644 --- a/STM32/STM32-F103ZET6/Src/main.c +++ b/STM32/STM32-F103ZET6/Src/main.c @@ -94,63 +94,7 @@ int main(void) MX_SPI1_Init(); /* USER CODE BEGIN 2 */ - // EPD_1in64g_test(); - // EPD_2in36g_test(); - // EPD_3in0g_test(); - // EPD_4in37g_test(); - // EPD_7in3g_test(); - - // EPD_1in02d_test(); - - // EPD_1in54_test(); - // EPD_1in54_V2_test(); - // EPD_1in54b_test(); - // EPD_1in54b_V2_test(); - // EPD_1in54c_test(); - - // EPD_2in7_test(); - // EPD_2in7b_test(); - // EPD_2in7b_V2_test(); - - // EPD_2in9_test(); - // EPD_2in9_V2_test(); - // EPD_2in9bc_test(); - // EPD_2in9b_V3_test(); - // EPD_2in9d_test(); - - // EPD_2in13_test(); - // EPD_2in13_V2_test(); - // EPD_2in13_V3_test(); - // EPD_2in13bc_test(); - // EPD_2in13b_V3_test(); - // EPD_2in13b_V4_test(); - // EPD_2in13d_test(); - - // EPD_2in66_test(); - // EPD_2in66b_test(); - - // EPD_3in52_test(); - // EPD_3in7_test(); - - // EPD_4in01f_test(); - - // EPD_4in2_test(); - // EPD_4in2bc_test(); - // EPD_4in2b_V2_test(); - // EPD_5in65f_test(); - - // EPD_5in83_test(); - // EPD_5in83_V2_test(); - // EPD_5in83bc_test(); - // EPD_5in83b_V2_test(); - - // EPD_7in5_test(); - // EPD_7in5_V2_test(); - // EPD_7in5bc_test(); - // EPD_7in5b_V2_test(); - - // EPD_7in5_HD_test(); - // EPD_7in5b_HD_test(); + EPD_test(); /* USER CODE END 2 */ diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_1in02_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_1in02_test.c index cd9de95..bf6b0a9 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_1in02_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_1in02_test.c @@ -31,7 +31,7 @@ #include "EPD_1in02d.h" #include -int EPD_1in02d_test(void) +int EPD_test(void) { printf("EPD_1IN02_test Demo\r\n"); if(DEV_Module_Init()!=0){ diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_1in54_V2_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_1in54_V2_test.c index dca98d5..b1521f6 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_1in54_V2_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_1in54_V2_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_1in54_V2.h" -int EPD_1in54_V2_test(void) +int EPD_test(void) { printf("EPD_1in54_V2_test Demo\r\n"); DEV_Module_Init(); diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_1in54_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_1in54_test.c index f493b14..e57759c 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_1in54_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_1in54_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_1in54.h" -int EPD_1in54_test(void) +int EPD_test(void) { printf("EPD_1IN54_test Demo\r\n"); DEV_Module_Init(); diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_1in54b_V2_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_1in54b_V2_test.c index 017897c..970c270 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_1in54b_V2_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_1in54b_V2_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_1in54b_V2.h" -int EPD_1in54b_V2_test(void) +int EPD_test(void) { printf("EPD_1IN54b_V2_test Demo\r\n"); if(DEV_Module_Init()!=0){ diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_1in54b_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_1in54b_test.c index bdef36a..e97d85f 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_1in54b_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_1in54b_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_1in54b.h" -int EPD_1in54b_test(void) +int EPD_test(void) { printf("EPD_1in54b_test Demo\r\n"); DEV_Module_Init(); diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_1in54c_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_1in54c_test.c index f4c26c2..44b0f30 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_1in54c_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_1in54c_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_1in54c.h" -int EPD_1in54c_test(void) +int EPD_test(void) { printf("EPD_1IN54C_test Demo\r\n"); DEV_Module_Init(); diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_1in64g_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_1in64g_test.c index 92e28e3..50648d2 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_1in64g_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_1in64g_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_1in64g.h" -int EPD_1in64g_test(void) +int EPD_test(void) { printf("EPD_1IN64G_test Demo\r\n"); if(DEV_Module_Init()!=0){ diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_2in13_V2_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_2in13_V2_test.c index c11418f..3e22994 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_2in13_V2_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_2in13_V2_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_2IN13_V2.h" -int EPD_2in13_V2_test(void) +int EPD_test(void) { printf("EPD_2IN13_V2_test Demo\r\n"); DEV_Module_Init(); diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_2in13_V3_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_2in13_V3_test.c index fce9c34..ce91959 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_2in13_V3_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_2in13_V3_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_2in13_V3.h" -int EPD_2in13_V3_test(void) +int EPD_test(void) { Debug("EPD_2in13_V3_test Demo\r\n"); if(DEV_Module_Init()!=0){ diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_2in13_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_2in13_test.c index dadb133..ca85f90 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_2in13_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_2in13_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_2in13.h" -int EPD_2in13_test(void) +int EPD_test(void) { printf("EPD_2IN13_test Demo\r\n"); DEV_Module_Init(); diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_2in13b_V3_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_2in13b_V3_test.c index fbb1303..27c969c 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_2in13b_V3_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_2in13b_V3_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_2IN13B_V3.h" -int EPD_2in13b_V3_test(void) +int EPD_test(void) { printf("EPD_2IN13B_V3_test Demo\r\n"); DEV_Module_Init(); diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_2in13b_V4_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_2in13b_V4_test.c index d815b40..7f8f0a5 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_2in13b_V4_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_2in13b_V4_test.c @@ -31,7 +31,7 @@ #include "EPD_Test.h" #include "EPD_2in13b_V4.h" -int EPD_2in13b_V4_test(void) +int EPD_test(void) { printf("EPD_2IN13B_V4_test Demo\r\n"); if(DEV_Module_Init()!=0){ diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_2in13bc_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_2in13bc_test.c index b3df782..f5daaa9 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_2in13bc_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_2in13bc_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_2IN13BC.h" -int EPD_2in13bc_test(void) +int EPD_test(void) { printf("EPD_2IN13BC_test Demo\r\n"); DEV_Module_Init(); diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_2in13d_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_2in13d_test.c index aaf68c9..138fabe 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_2in13d_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_2in13d_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_2in13d.h" -int EPD_2in13d_test(void) +int EPD_test(void) { printf("EPD_2IN13D_test Demo\r\n"); DEV_Module_Init(); diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_2in36g_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_2in36g_test.c index 390f032..195dbcc 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_2in36g_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_2in36g_test.c @@ -31,7 +31,7 @@ #include "EPD_2in36g.h" #include "time.h" -int EPD_2in36g_test(void) +int EPD_test(void) { printf("EPD_2IN36G_test Demo\r\n"); if(DEV_Module_Init()!=0){ diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_2in66_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_2in66_test.c index 7e88972..03cd8a3 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_2in66_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_2in66_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_2in66.h" -int EPD_2in66_test(void) +int EPD_test(void) { printf("EPD_2IN66_test Demo\r\n"); if(DEV_Module_Init()!=0){ diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_2in66b_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_2in66b_test.c index 4f130fe..92c4301 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_2in66b_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_2in66b_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_2in66b.h" -int EPD_2in66b_test(void) +int EPD_test(void) { printf("EPD_2IN66B_test Demo\r\n"); if(DEV_Module_Init()!=0){ diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_2in7_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_2in7_test.c index 51d136c..78ac2fb 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_2in7_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_2in7_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_2in7.h" -int EPD_2in7_test(void) +int EPD_test(void) { printf("EPD_2IN7_test Demo\r\n"); DEV_Module_Init(); diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_2in7b_V2_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_2in7b_V2_test.c index 53b2c30..1c755e5 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_2in7b_V2_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_2in7b_V2_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_2in7b_V2.h" -int EPD_2in7b_V2_test(void) +int EPD_test(void) { printf("EPD_2IN7B_V2_test Demo\r\n"); if(DEV_Module_Init()!=0){ diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_2in7b_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_2in7b_test.c index 6470ab6..ff9160e 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_2in7b_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_2in7b_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_2IN7b.h" -int EPD_2in7b_test(void) +int EPD_test(void) { printf("EPD_2IN7B_test Demo\r\n"); DEV_Module_Init(); diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_2in9_V2_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_2in9_V2_test.c index a7dbe1a..1a2470d 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_2in9_V2_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_2in9_V2_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_2in9_V2.h" -int EPD_2in9_V2_test(void) +int EPD_test(void) { printf("EPD_2IN9_V2_test Demo\r\n"); if(DEV_Module_Init()!=0){ diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_2in9_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_2in9_test.c index 5c6e298..ab7c8f9 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_2in9_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_2in9_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_2in9.h" -int EPD_2in9_test(void) +int EPD_test(void) { printf("EPD_2IN9_test Demo\r\n"); DEV_Module_Init(); diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_2in9b_V3_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_2in9b_V3_test.c index 6d3720b..7a5099b 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_2in9b_V3_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_2in9b_V3_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_2IN9B_V3.h" -int EPD_2in9b_V3_test(void) +int EPD_test(void) { printf("EPD_2IN9B_V3_test Demo\r\n"); DEV_Module_Init(); diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_2in9bc_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_2in9bc_test.c index fa7689d..72824dc 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_2in9bc_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_2in9bc_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_2IN9BC.h" -int EPD_2in9bc_test(void) +int EPD_test(void) { printf("EPD_2IN9BC_test Demo\r\n"); DEV_Module_Init(); diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_2in9d_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_2in9d_test.c index 79bd5e5..b2f16a9 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_2in9d_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_2in9d_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_2in9d.h" -int EPD_2in9d_test(void) +int EPD_test(void) { printf("EPD_2IN9D_test Demo\r\n"); DEV_Module_Init(); diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_3in0g_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_3in0g_test.c index 2502639..b8af2be 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_3in0g_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_3in0g_test.c @@ -31,7 +31,7 @@ #include "EPD_3in0g.h" #include "time.h" -int EPD_3in0g_test(void) +int EPD_test(void) { printf("EPD_3IN0G_test Demo\r\n"); if(DEV_Module_Init()!=0){ diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_3in52_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_3in52_test.c index e717679..785736d 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_3in52_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_3in52_test.c @@ -31,7 +31,7 @@ #include "EPD_3in52.h" #include -int EPD_3in52_test(void) +int EPD_test(void) { printf("EPD_3IN52_test Demo\r\n"); if(DEV_Module_Init()!=0){ @@ -66,7 +66,7 @@ int EPD_3in52_test(void) #if 1 // GC waveform refresh Paint_SelectImage(BlackImage); Paint_Clear(WHITE); - Paint_DrawBitMap(gImage_3in52); + Paint_DrawBitMap(gImage_3in52); EPD_3IN52_display(BlackImage); EPD_3IN52_lut_GC(); @@ -80,7 +80,7 @@ int EPD_3in52_test(void) printf("Quick refresh is supported, but the refresh effect is not good, but it is not recommended\r\n"); Paint_SelectImage(BlackImage); Paint_Clear(WHITE); - Paint_DrawBitMap(gImage_3in52); + Paint_DrawBitMap(gImage_3in52); EPD_3IN52_display(BlackImage); EPD_3IN52_lut_DU(); diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_3in7_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_3in7_test.c index 49968c8..df03678 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_3in7_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_3in7_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_3in7.h" -int EPD_3in7_test(void) +int EPD_test(void) { printf("EPD_3IN7_test Demo\r\n"); if(DEV_Module_Init()!=0){ diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_4in01f_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_4in01f_test.c index ccbc7b1..1e4847d 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_4in01f_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_4in01f_test.c @@ -30,7 +30,7 @@ #include "EPD_4IN01F.h" #include "EPD_Test.h" -int EPD_4in01f_test(void) +int EPD_test(void) { printf("EPD_4in01f_test Demo\r\n"); if(DEV_Module_Init()!=0){ diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_4in2_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_4in2_test.c index ab1a164..a59ab8c 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_4in2_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_4in2_test.c @@ -31,7 +31,7 @@ #include "EPD_4in2.h" #include -int EPD_4in2_test(void) +int EPD_test(void) { printf("EPD_4IN2_test Demo\r\n"); if(DEV_Module_Init()!=0){ @@ -86,8 +86,8 @@ int EPD_4in2_test(void) Paint_DrawString_EN(10, 20, "hello world", &Font12, WHITE, BLACK); Paint_DrawNum(10, 33, 123456789, &Font12, BLACK, WHITE); Paint_DrawNum(10, 50, 987654321, &Font16, WHITE, BLACK); - Paint_DrawString_CN(130, 0, " ���abc", &Font12CN, BLACK, WHITE); - Paint_DrawString_CN(130, 20, "΢ѩ����", &Font24CN, WHITE, BLACK); + Paint_DrawString_CN(130, 0, "abc", &Font12CN, BLACK, WHITE); + Paint_DrawString_CN(130, 20, "΢ѩ", &Font24CN, WHITE, BLACK); printf("EPD_Display\r\n"); EPD_4IN2_Display(BlackImage); @@ -156,15 +156,15 @@ int EPD_4in2_test(void) Paint_DrawString_EN(10, 20, "hello world", &Font12, WHITE, BLACK); Paint_DrawNum(10, 33, 123456789, &Font12, BLACK, WHITE); Paint_DrawNum(10, 50, 987654321, &Font16, WHITE, BLACK); - Paint_DrawString_CN(140, 0, "���abc", &Font12CN, GRAY1, GRAY4); - Paint_DrawString_CN(140, 40, "���abc", &Font12CN, GRAY2, GRAY3); - Paint_DrawString_CN(140, 80, "���abc", &Font12CN, GRAY3, GRAY2); - Paint_DrawString_CN(140, 120, "���abc", &Font12CN, GRAY4, GRAY1); + Paint_DrawString_CN(140, 0, "abc", &Font12CN, GRAY1, GRAY4); + Paint_DrawString_CN(140, 40, "abc", &Font12CN, GRAY2, GRAY3); + Paint_DrawString_CN(140, 80, "abc", &Font12CN, GRAY3, GRAY2); + Paint_DrawString_CN(140, 120, "abc", &Font12CN, GRAY4, GRAY1); - Paint_DrawString_CN(220, 0, "΢ѩ����", &Font24CN, GRAY1, GRAY4); - Paint_DrawString_CN(220, 40, "΢ѩ����", &Font24CN, GRAY2, GRAY3); - Paint_DrawString_CN(220, 80, "΢ѩ����", &Font24CN, GRAY3, GRAY2); - Paint_DrawString_CN(220, 120, "΢ѩ����", &Font24CN, GRAY4, GRAY1); + Paint_DrawString_CN(220, 0, "΢ѩ", &Font24CN, GRAY1, GRAY4); + Paint_DrawString_CN(220, 40, "΢ѩ", &Font24CN, GRAY2, GRAY3); + Paint_DrawString_CN(220, 80, "΢ѩ", &Font24CN, GRAY3, GRAY2); + Paint_DrawString_CN(220, 120, "΢ѩ", &Font24CN, GRAY4, GRAY1); EPD_4IN2_4GrayDisplay(BlackImage); DEV_Delay_ms(500); diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_4in2b_V2_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_4in2b_V2_test.c index f32995e..1bdc81e 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_4in2b_V2_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_4in2b_V2_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_4in2b_V2.h" -int EPD_4in2b_V2_test(void) +int EPD_test(void) { printf("EPD_4IN2B_V2_test Demo\r\n"); if(DEV_Module_Init()!=0){ diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_4in2bc_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_4in2bc_test.c index e35ae3a..fe6238c 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_4in2bc_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_4in2bc_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_4in2bc.h" -int EPD_4in2bc_test(void) +int EPD_test(void) { printf("EPD_4IN2BC_test Demo\r\n"); DEV_Module_Init(); diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_4in37g_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_4in37g_test.c index a9d73d3..de4d8ad 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_4in37g_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_4in37g_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_4in37g.h" -int EPD_4in37g_test(void) +int EPD_test(void) { printf("EPD_4IN37G_test Demo\r\n"); if(DEV_Module_Init()!=0){ diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_5in65f_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_5in65f_test.c index aa2263e..e4cb3fb 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_5in65f_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_5in65f_test.c @@ -30,7 +30,7 @@ #include "EPD_5in65f.h" #include "EPD_Test.h" -int EPD_5in65f_test(void) +int EPD_test(void) { printf("EPD_5in65F_test Demo\r\n"); if(DEV_Module_Init()!=0){ diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_5in83_V2_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_5in83_V2_test.c index 80f1d17..93c47df 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_5in83_V2_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_5in83_V2_test.c @@ -31,7 +31,7 @@ #include "EPD_5in83_V2.h" #include "time.h" -int EPD_5in83_V2_test(void) +int EPD_test(void) { printf("EPD_5IN83_V2_test Demo\r\n"); if(DEV_Module_Init()!=0){ diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_5in83_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_5in83_test.c index 44c4cd2..922ff9a 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_5in83_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_5in83_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_5in83.h" -int EPD_5in83_test(void) +int EPD_test(void) { printf("EPD_5IN83_test Demo\r\n"); DEV_Module_Init(); diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_5in83b_V2_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_5in83b_V2_test.c index a83021a..4055e74 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_5in83b_V2_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_5in83b_V2_test.c @@ -31,7 +31,7 @@ #include "EPD_5in83b_V2.h" #include "ImageData.h" -int EPD_5in83b_V2_test(void) +int EPD_test(void) { printf("EPD_5in83b_V2_test Demo\r\n"); DEV_Module_Init(); diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_5in83bc_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_5in83bc_test.c index 424ed92..79c6325 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_5in83bc_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_5in83bc_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_5in83bc.h" -int EPD_5in83bc_test(void) +int EPD_test(void) { printf("EPD_5IN83BC_test Demo\r\n"); DEV_Module_Init(); diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_7in3g_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_7in3g_test.c index ca66d9a..c57ba25 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_7in3g_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_7in3g_test.c @@ -31,7 +31,7 @@ #include "EPD_7in3g.h" #include "time.h" -int EPD_7in3g_test(void) +int EPD_test(void) { printf("EPD_7IN3G_test Demo\r\n"); if(DEV_Module_Init()!=0){ diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_7in5_HD_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_7in5_HD_test.c index e24427c..d863e9f 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_7in5_HD_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_7in5_HD_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_7in5_HD.h" -int EPD_7in5_HD_test(void) +int EPD_test(void) { printf("EPD_7IN5_HD_test Demo\r\n"); if(DEV_Module_Init()!=0){ @@ -58,13 +58,13 @@ int EPD_7in5_HD_test(void) Paint_SelectImage(BlackImage); Paint_Clear(WHITE); //Paint_DrawBitMap(gImage_7in5_V2); - //EPD_7IN5_HD_WritePicture(BlackImage, 0); - //The entire image size is EPD_7IN5_HD_WIDTH*EPD_7IN5_HD_HEIGHT/8 - //Since the memory problem is transmitted halfway, now the other half is transmitted, so the offset address is required. - //Paint_DrawBitMap(gImage_7in5_V2 + EPD_7IN5_HD_WIDTH*EPD_7IN5_HD_HEIGHT/8/2); - //EPD_7IN5_HD_WritePicture(BlackImage, 1); + //EPD_7IN5_HD_WritePicture(BlackImage, 0); + //The entire image size is EPD_7IN5_HD_WIDTH*EPD_7IN5_HD_HEIGHT/8 + //Since the memory problem is transmitted halfway, now the other half is transmitted, so the offset address is required. + //Paint_DrawBitMap(gImage_7in5_V2 + EPD_7IN5_HD_WIDTH*EPD_7IN5_HD_HEIGHT/8/2); + //EPD_7IN5_HD_WritePicture(BlackImage, 1); - EPD_7IN5_HD_DisplayImage(gImage_7in5_V2,0,0,800,480); + EPD_7IN5_HD_DisplayImage(gImage_7in5_V2,0,0,800,480); DEV_Delay_ms(2000); #endif @@ -93,9 +93,9 @@ int EPD_7in5_HD_test(void) Paint_DrawNum(10, 50, 987654321, &Font16, WHITE, BLACK); Paint_DrawString_CN(130, 0, " abc", &Font12CN, BLACK, WHITE); Paint_DrawString_CN(130, 20, "΢ѩ", &Font24CN, WHITE, BLACK); - EPD_7IN5_HD_WritePicture(BlackImage, 0); - Paint_Clear(WHITE); - EPD_7IN5_HD_WritePicture(BlackImage, 1); + EPD_7IN5_HD_WritePicture(BlackImage, 0); + Paint_Clear(WHITE); + EPD_7IN5_HD_WritePicture(BlackImage, 1); printf("EPD_Display\r\n"); DEV_Delay_ms(2000); #endif diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_7in5_V2_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_7in5_V2_test.c index 780f757..48d102f 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_7in5_V2_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_7in5_V2_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_7in5_V2.h" -int EPD_7in5_V2_test(void) +int EPD_test(void) { printf("EPD_7IN5_V2_test Demo\r\n"); if(DEV_Module_Init()!=0){ @@ -58,11 +58,11 @@ int EPD_7in5_V2_test(void) Paint_SelectImage(BlackImage); Paint_Clear(WHITE); Paint_DrawBitMap(gImage_7in5_V2); - EPD_7IN5_V2_WritePicture(BlackImage, 0); - //The entire image size is EPD_7IN5_V2_WIDTH*EPD_7IN5_V2_HEIGHT/8 - //Since the memory problem is transmitted halfway, now the other half is transmitted, so the offset address is required. - Paint_DrawBitMap(gImage_7in5_V2 + EPD_7IN5_V2_WIDTH*EPD_7IN5_V2_HEIGHT/8/2); - EPD_7IN5_V2_WritePicture(BlackImage, 1); + EPD_7IN5_V2_WritePicture(BlackImage, 0); + //The entire image size is EPD_7IN5_V2_WIDTH*EPD_7IN5_V2_HEIGHT/8 + //Since the memory problem is transmitted halfway, now the other half is transmitted, so the offset address is required. + Paint_DrawBitMap(gImage_7in5_V2 + EPD_7IN5_V2_WIDTH*EPD_7IN5_V2_HEIGHT/8/2); + EPD_7IN5_V2_WritePicture(BlackImage, 1); DEV_Delay_ms(2000); #endif @@ -91,9 +91,9 @@ int EPD_7in5_V2_test(void) Paint_DrawNum(10, 50, 987654321, &Font16, WHITE, BLACK); Paint_DrawString_CN(130, 0, " abc", &Font12CN, BLACK, WHITE); Paint_DrawString_CN(130, 20, "΢ѩ", &Font24CN, WHITE, BLACK); - EPD_7IN5_V2_WritePicture(BlackImage, 0); - Paint_Clear(WHITE); - EPD_7IN5_V2_WritePicture(BlackImage, 1); + EPD_7IN5_V2_WritePicture(BlackImage, 0); + Paint_Clear(WHITE); + EPD_7IN5_V2_WritePicture(BlackImage, 1); printf("EPD_Display\r\n"); DEV_Delay_ms(2000); #endif diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_7in5_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_7in5_test.c index 486f8b1..dde6e42 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_7in5_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_7in5_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_7in5.h" -int EPD_7in5_test(void) +int EPD_test(void) { printf("EPD_7IN5_test Demo\r\n"); DEV_Module_Init(); diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_7in5b_HD_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_7in5b_HD_test.c index 8977007..e9be3ad 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_7in5b_HD_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_7in5b_HD_test.c @@ -31,7 +31,7 @@ #include "EPD_7in5b_HD.h" #include "ImageData.h" -int EPD_7in5b_HD_test(void) +int EPD_test(void) { printf("EPD_7IN5B_HD_test Demo\r\n"); if(DEV_Module_Init()!=0){ @@ -81,8 +81,8 @@ int EPD_7in5b_HD_test(void) Paint_DrawString_CN(130, 20, "΢ѩ", &Font24CN, WHITE, BLACK); Paint_DrawNum(10, 50, 987654321, &Font16, WHITE, BLACK); EPD_7IN5B_HD_DisplayPicture(BlackImage,0); - Paint_Clear(WHITE); - EPD_7IN5B_HD_DisplayPicture(BlackImage,1); + Paint_Clear(WHITE); + EPD_7IN5B_HD_DisplayPicture(BlackImage,1); //2.Draw red image Paint_Clear(WHITE); Paint_DrawCircle(160, 95, 20, BLACK, DOT_PIXEL_1X1, DRAW_FILL_EMPTY); @@ -93,9 +93,9 @@ int EPD_7in5b_HD_test(void) Paint_DrawString_EN(10, 20, "hello world", &Font12, WHITE, BLACK); Paint_DrawNum(10, 33, 123456789, &Font12, BLACK, WHITE); EPD_7IN5B_HD_DisplayPicture(BlackImage,2); - Paint_Clear(WHITE); - printf("EPD_Display\r\n"); - EPD_7IN5B_HD_DisplayPicture(BlackImage,3); + Paint_Clear(WHITE); + printf("EPD_Display\r\n"); + EPD_7IN5B_HD_DisplayPicture(BlackImage,3); DEV_Delay_ms(5000); #endif diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_7in5b_V2_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_7in5b_V2_test.c index a65482c..e106e5d 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_7in5b_V2_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_7in5b_V2_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_7in5b_V2.h" -int EPD_7in5b_V2_test(void) +int EPD_test(void) { printf("EPD_7IN5B_V2_test Demo\r\n"); DEV_Module_Init(); diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_7in5bc_test.c b/STM32/STM32-F103ZET6/User/Examples/EPD_7in5bc_test.c index faf6d8a..df99568 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_7in5bc_test.c +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_7in5bc_test.c @@ -30,7 +30,7 @@ #include "EPD_Test.h" #include "EPD_7in5bc.h" -int EPD_7in5bc_test(void) +int EPD_test(void) { printf("EPD_7IN5BC_test Demo\r\n"); DEV_Module_Init(); diff --git a/STM32/STM32-F103ZET6/User/Examples/EPD_Test.h b/STM32/STM32-F103ZET6/User/Examples/EPD_Test.h index dd5925e..4d630de 100644 --- a/STM32/STM32-F103ZET6/User/Examples/EPD_Test.h +++ b/STM32/STM32-F103ZET6/User/Examples/EPD_Test.h @@ -36,62 +36,6 @@ #include "Debug.h" #include // malloc() free() -int EPD_1in64g_test(void); -int EPD_2in36g_test(void); -int EPD_3in0g_test(void); -int EPD_4in37g_test(void); -int EPD_7in3g_test(void); +int EPD_test(void); -int EPD_1in02d_test(void); - -int EPD_1in54_test(void); -int EPD_1in54_V2_test(void); -int EPD_1in54b_test(void); -int EPD_1in54b_V2_test(void); -int EPD_1in54c_test(void); - -int EPD_2in7_test(void); -int EPD_2in7b_test(void); -int EPD_2in7b_V2_test(void); - -int EPD_2in9_test(void); -int EPD_2in9_V2_test(void); -int EPD_2in9bc_test(void); -int EPD_2in9b_V3_test(void); -int EPD_2in9d_test(void); - -int EPD_2in13_test(void); -int EPD_2in13_V2_test(void); -int EPD_2in13_V3_test(void); -int EPD_2in13bc_test(void); -int EPD_2in13b_V3_test(void); -int EPD_2in13b_V4_test(void); -int EPD_2in13d_test(void); - -int EPD_2in66_test(void); -int EPD_2in66b_test(void); - -int EPD_3in52_test(void); -int EPD_3in7_test(void); - -int EPD_4in01f_test(void); - -int EPD_4in2_test(void); -int EPD_4in2bc_test(void); -int EPD_4in2b_V2_test(void); - -int EPD_5in65f_test(void); - -int EPD_5in83_test(void); -int EPD_5in83_V2_test(void); -int EPD_5in83bc_test(void); -int EPD_5in83b_V2_test(void); - -int EPD_7in5_test(void); -int EPD_7in5_V2_test(void); -int EPD_7in5bc_test(void); -int EPD_7in5b_V2_test(void); - -int EPD_7in5_HD_test(void); -int EPD_7in5b_HD_test(void); #endif diff --git a/STM32/STM32-F103ZET6/User/Examples/ImageData2.c b/STM32/STM32-F103ZET6/User/Examples/ImageData2.c index fade666..dad8a74 100644 --- a/STM32/STM32-F103ZET6/User/Examples/ImageData2.c +++ b/STM32/STM32-F103ZET6/User/Examples/ImageData2.c @@ -4,7 +4,7 @@ * | Function : *---------------- * | This version: V1.0 -* | Date : 2022-4-25 +* | Date : 2022- 4-25 * | Info : * # @@ -11764,4 +11764,7 @@ const unsigned char gImage_4in37g[47104] = { 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, -}; \ No newline at end of file +}; + + + diff --git a/STM32/STM32-F103ZET6/User/e-Paper/EPD_1in64g.c b/STM32/STM32-F103ZET6/User/e-Paper/EPD_1in64g.c index 3872795..dc3d3eb 100644 --- a/STM32/STM32-F103ZET6/User/e-Paper/EPD_1in64g.c +++ b/STM32/STM32-F103ZET6/User/e-Paper/EPD_1in64g.c @@ -83,14 +83,6 @@ static void EPD_1IN64G_ReadBusyH(void) } Debug("e-Paper busy H release\r\n"); } -static void EPD_1IN64G_ReadBusyL(void) -{ - Debug("e-Paper busy L\r\n"); - while(DEV_Digital_Read(EPD_BUSY_PIN)) { //LOW: idle, HIGH: busy - DEV_Delay_ms(5); - } - Debug("e-Paper busy L release\r\n"); -} /****************************************************************************** function : Turn On Display diff --git a/STM32/STM32-F103ZET6/User/e-Paper/EPD_2in36g.c b/STM32/STM32-F103ZET6/User/e-Paper/EPD_2in36g.c index 1ea6a71..a2c0258 100644 --- a/STM32/STM32-F103ZET6/User/e-Paper/EPD_2in36g.c +++ b/STM32/STM32-F103ZET6/User/e-Paper/EPD_2in36g.c @@ -83,14 +83,6 @@ static void EPD_2IN36G_ReadBusyH(void) } Debug("e-Paper busy H release\r\n"); } -static void EPD_2IN36G_ReadBusyL(void) -{ - Debug("e-Paper busy L\r\n"); - while(DEV_Digital_Read(EPD_BUSY_PIN)) { //LOW: idle, HIGH: busy - DEV_Delay_ms(5); - } - Debug("e-Paper busy L release\r\n"); -} /****************************************************************************** function : Turn On Display diff --git a/STM32/STM32-F103ZET6/User/e-Paper/EPD_2in7.c b/STM32/STM32-F103ZET6/User/e-Paper/EPD_2in7.c index 64784a9..b0ffc0a 100644 --- a/STM32/STM32-F103ZET6/User/e-Paper/EPD_2in7.c +++ b/STM32/STM32-F103ZET6/User/e-Paper/EPD_2in7.c @@ -287,28 +287,28 @@ void EPD_2in7_gray_SetLut(void) { unsigned int count; EPD_2in7_SendCommand(0x20); //vcom - for(count=0;count<44;count++) - {EPD_2in7_SendData(EPD_2in7_gray_lut_vcom[count]);} + for(count=0;count<44;count++) + {EPD_2in7_SendData(EPD_2in7_gray_lut_vcom[count]);} EPD_2in7_SendCommand(0x21); //red not use for(count=0;count<42;count++) - {EPD_2in7_SendData(EPD_2in7_gray_lut_ww[count]);} + {EPD_2in7_SendData(EPD_2in7_gray_lut_ww[count]);} - EPD_2in7_SendCommand(0x22); //bw r - for(count=0;count<42;count++) - {EPD_2in7_SendData(EPD_2in7_gray_lut_bw[count]);} + EPD_2in7_SendCommand(0x22); //bw r + for(count=0;count<42;count++) + {EPD_2in7_SendData(EPD_2in7_gray_lut_bw[count]);} - EPD_2in7_SendCommand(0x23); //wb w - for(count=0;count<42;count++) - {EPD_2in7_SendData(EPD_2in7_gray_lut_wb[count]);} + EPD_2in7_SendCommand(0x23); //wb w + for(count=0;count<42;count++) + {EPD_2in7_SendData(EPD_2in7_gray_lut_wb[count]);} - EPD_2in7_SendCommand(0x24); //bb b - for(count=0;count<42;count++) - {EPD_2in7_SendData(EPD_2in7_gray_lut_bb[count]);} + EPD_2in7_SendCommand(0x24); //bb b + for(count=0;count<42;count++) + {EPD_2in7_SendData(EPD_2in7_gray_lut_bb[count]);} - EPD_2in7_SendCommand(0x25); //vcom - for(count=0;count<42;count++) - {EPD_2in7_SendData(EPD_2in7_gray_lut_ww[count]);} + EPD_2in7_SendCommand(0x25); //vcom + for(count=0;count<42;count++) + {EPD_2in7_SendData(EPD_2in7_gray_lut_ww[count]);} } diff --git a/STM32/STM32-F103ZET6/User/e-Paper/EPD_2in9bc.c b/STM32/STM32-F103ZET6/User/e-Paper/EPD_2in9bc.c index ec498da..5c33f94 100644 --- a/STM32/STM32-F103ZET6/User/e-Paper/EPD_2in9bc.c +++ b/STM32/STM32-F103ZET6/User/e-Paper/EPD_2in9bc.c @@ -193,8 +193,8 @@ void EPD_2IN9BC_Clear(void) } } - EPD_2IN9BC_SendCommand(0x12); - EPD_2IN9BC_ReadBusy(); + EPD_2IN9BC_SendCommand(0x12); + EPD_2IN9BC_ReadBusy(); } /****************************************************************************** diff --git a/STM32/STM32-F103ZET6/User/e-Paper/EPD_3in0g.c b/STM32/STM32-F103ZET6/User/e-Paper/EPD_3in0g.c index 4383788..ce76874 100644 --- a/STM32/STM32-F103ZET6/User/e-Paper/EPD_3in0g.c +++ b/STM32/STM32-F103ZET6/User/e-Paper/EPD_3in0g.c @@ -83,14 +83,6 @@ static void EPD_3IN0G_ReadBusyH(void) } Debug("e-Paper busy H release\r\n"); } -static void EPD_3IN0G_ReadBusyL(void) -{ - Debug("e-Paper busy L\r\n"); - while(DEV_Digital_Read(EPD_BUSY_PIN)) { //LOW: idle, HIGH: busy - DEV_Delay_ms(5); - } - Debug("e-Paper busy L release\r\n"); -} /****************************************************************************** function : Turn On Display diff --git a/STM32/STM32-F103ZET6/User/e-Paper/EPD_4in2.c b/STM32/STM32-F103ZET6/User/e-Paper/EPD_4in2.c index f7919d9..ab136c9 100644 --- a/STM32/STM32-F103ZET6/User/e-Paper/EPD_4in2.c +++ b/STM32/STM32-F103ZET6/User/e-Paper/EPD_4in2.c @@ -609,11 +609,10 @@ void EPD_4IN2_Display(UBYTE *Image) void EPD_4IN2_PartialDisplay(UWORD X_start,UWORD Y_start,UWORD X_end,UWORD Y_end, UBYTE *Image) { - UWORD Width, Height; + UWORD Width; static UBYTE DATA[EPD_4IN2_WIDTH * EPD_4IN2_HEIGHT / 8] = {0x00}; Width = (EPD_4IN2_WIDTH % 8 == 0)? (EPD_4IN2_WIDTH / 8 ): (EPD_4IN2_WIDTH / 8 + 1); - Height = EPD_4IN2_HEIGHT; X_start = (X_start % 8 == 0)? (X_start): (X_start/8*8+8); X_end = (X_end % 8 == 0)? (X_end): (X_end/8*8+8); diff --git a/STM32/STM32-F103ZET6/User/e-Paper/EPD_4in37g.c b/STM32/STM32-F103ZET6/User/e-Paper/EPD_4in37g.c index cc12405..92af690 100644 --- a/STM32/STM32-F103ZET6/User/e-Paper/EPD_4in37g.c +++ b/STM32/STM32-F103ZET6/User/e-Paper/EPD_4in37g.c @@ -83,14 +83,6 @@ static void EPD_4IN37G_ReadBusyH(void) } Debug("e-Paper busy H release\r\n"); } -static void EPD_4IN37G_ReadBusyL(void) -{ - Debug("e-Paper busy L\r\n"); - while(DEV_Digital_Read(EPD_BUSY_PIN)) { //LOW: idle, HIGH: busy - DEV_Delay_ms(5); - } - Debug("e-Paper busy L release\r\n"); -} /****************************************************************************** function : Turn On Display diff --git a/STM32/STM32-F103ZET6/User/e-Paper/EPD_7in3g.c b/STM32/STM32-F103ZET6/User/e-Paper/EPD_7in3g.c index aa12a02..36f23a5 100644 --- a/STM32/STM32-F103ZET6/User/e-Paper/EPD_7in3g.c +++ b/STM32/STM32-F103ZET6/User/e-Paper/EPD_7in3g.c @@ -83,14 +83,6 @@ static void EPD_7IN3G_ReadBusyH(void) } Debug("e-Paper busy H release\r\n"); } -static void EPD_7IN3G_ReadBusyL(void) -{ - Debug("e-Paper busy L\r\n"); - while(DEV_Digital_Read(EPD_BUSY_PIN)) { //LOW: idle, HIGH: busy - DEV_Delay_ms(5); - } - Debug("e-Paper busy L release\r\n"); -} /****************************************************************************** function : Turn On Display diff --git a/STM32/STM32-F103ZET6/User/e-Paper/EPD_7in5.c b/STM32/STM32-F103ZET6/User/e-Paper/EPD_7in5.c index 2ea6514..c95d9ad 100644 --- a/STM32/STM32-F103ZET6/User/e-Paper/EPD_7in5.c +++ b/STM32/STM32-F103ZET6/User/e-Paper/EPD_7in5.c @@ -160,7 +160,7 @@ void EPD_7IN5_Init(void) { EPD_7IN5_Reset(); - EPD_7IN5_SendCommand(0x01); // POWER_SETTING + EPD_7IN5_SendCommand(0x01); // POWER_SETTING EPD_7IN5_SendData(0x37); EPD_7IN5_SendData(0x00); diff --git a/STM32/STM32-F103ZET6/User/e-Paper/EPD_7in5b_HD.c b/STM32/STM32-F103ZET6/User/e-Paper/EPD_7in5b_HD.c index 931c7a1..94f32d2 100644 --- a/STM32/STM32-F103ZET6/User/e-Paper/EPD_7in5b_HD.c +++ b/STM32/STM32-F103ZET6/User/e-Paper/EPD_7in5b_HD.c @@ -280,31 +280,30 @@ void EPD_7IN5B_HD_DisplayPicture(const UBYTE *blackimage,UBYTE Block) EPD_7IN5B_HD_SendData(0xAF); EPD_7IN5B_HD_SendData(0x02); EPD_7IN5B_HD_SendCommand(0x24); - for (UDOUBLE j = 0; j < Height/2; j++) { - for (UDOUBLE i = 0; i < Width; i++) { - EPD_7IN5B_HD_SendData(blackimage[i + j * Width]); - } - } - + for (UDOUBLE j = 0; j < Height/2; j++) { + for (UDOUBLE i = 0; i < Width; i++) { + EPD_7IN5B_HD_SendData(blackimage[i + j * Width]); + } + } }else if(Block == 1){ for (UDOUBLE j = 0; j < Height/2; j++) { - for (UDOUBLE i = 0; i < Width; i++) { - EPD_7IN5B_HD_SendData(blackimage[i + j * Width]); + for (UDOUBLE i = 0; i < Width; i++) { + EPD_7IN5B_HD_SendData(blackimage[i + j * Width]); + } } - } }else if(Block == 2){ EPD_7IN5B_HD_SendCommand(0x26); - for (UDOUBLE j = 0; j < Height/2; j++) { - for (UDOUBLE i = 0; i < Width; i++) { - EPD_7IN5B_HD_SendData(~blackimage[i + j * Width]); + for (UDOUBLE j = 0; j < Height/2; j++) { + for (UDOUBLE i = 0; i < Width; i++) { + EPD_7IN5B_HD_SendData(~blackimage[i + j * Width]); + } } - } }else if(Block == 3){ for (UDOUBLE j = 0; j < Height/2; j++) { - for (UDOUBLE i = 0; i < Width; i++) { - EPD_7IN5B_HD_SendData(~blackimage[i + j * Width]); + for (UDOUBLE i = 0; i < Width; i++) { + EPD_7IN5B_HD_SendData(~blackimage[i + j * Width]); + } } - } EPD_7IN5B_HD_TurnOnDisplay(); } } @@ -327,12 +326,11 @@ void EPD_7IN5B_HD_DisplayImage(const UBYTE *blackimage, const UBYTE *ryimage,UDO EPD_7IN5B_HD_SendCommand(0x24); for (UDOUBLE j = 0; j < Height; j++) { for (UDOUBLE i = 0; i < Width; i++) { - if((i>=start_X/8) && (i<(start_X+image_width)/8) && (j>=start_Y) && (j<(start_Y+image_high))){ - EPD_7IN5B_HD_SendData(blackimage[i-start_X/8 + (j - start_Y) * image_width/8]); - }else{ - EPD_7IN5B_HD_SendData(0xff); - } - + if((i>=start_X/8) && (i<(start_X+image_width)/8) && (j>=start_Y) && (j<(start_Y+image_high))){ + EPD_7IN5B_HD_SendData(blackimage[i-start_X/8 + (j - start_Y) * image_width/8]); + }else{ + EPD_7IN5B_HD_SendData(0xff); + } } } @@ -341,12 +339,11 @@ void EPD_7IN5B_HD_DisplayImage(const UBYTE *blackimage, const UBYTE *ryimage,UDO EPD_7IN5B_HD_SendCommand(0x26); for (UDOUBLE j = 0; j < Height; j++) { for (UDOUBLE i = 0; i < Width; i++) { - if((i>=start_X/8) && (i<(start_X+image_width)/8) && (j>=start_Y) && (j<(start_Y+image_high))){ - EPD_7IN5B_HD_SendData(~ryimage[i-start_X/8 + (j - start_Y) * image_width/8]); - }else{ - EPD_7IN5B_HD_SendData(0x00); - } - + if((i>=start_X/8) && (i<(start_X+image_width)/8) && (j>=start_Y) && (j<(start_Y+image_high))){ + EPD_7IN5B_HD_SendData(~ryimage[i-start_X/8 + (j - start_Y) * image_width/8]); + }else{ + EPD_7IN5B_HD_SendData(0x00); + } } } EPD_7IN5B_HD_TurnOnDisplay(); From 1e51790b89ed0999e9f0209c7ce306ad16192bbf Mon Sep 17 00:00:00 2001 From: SSYYL <1032789891@qq.com> Date: Thu, 13 Oct 2022 11:58:25 +0800 Subject: [PATCH 2/2] Modify the compilation logic to speed up the first compilation and simplify operations. --- RaspberryPi_JetsonNano/c/Makefile | 219 +++++++++++++-- RaspberryPi_JetsonNano/c/Makefile.save | 82 ------ RaspberryPi_JetsonNano/c/examples/main.c | 260 +++++++++--------- .../c/lib/e-Paper/EPD_1in64g.c | 8 - .../c/lib/e-Paper/EPD_2in36g.c | 8 - .../c/lib/e-Paper/EPD_3in0g.c | 8 - .../c/lib/e-Paper/EPD_4in37g.c | 8 - .../c/lib/e-Paper/EPD_7in3g.c | 8 - RaspberryPi_JetsonNano/c/list.txt | 74 ++--- RaspberryPi_JetsonNano/c/readme_CN.txt | 16 +- RaspberryPi_JetsonNano/c/readme_EN.txt | 16 +- 11 files changed, 376 insertions(+), 331 deletions(-) delete mode 100644 RaspberryPi_JetsonNano/c/Makefile.save diff --git a/RaspberryPi_JetsonNano/c/Makefile b/RaspberryPi_JetsonNano/c/Makefile index 77393f2..e8abd04 100644 --- a/RaspberryPi_JetsonNano/c/Makefile +++ b/RaspberryPi_JetsonNano/c/Makefile @@ -1,11 +1,179 @@ -DIR_Config = ./lib/Config -DIR_EPD = ./lib/e-Paper -DIR_FONTS = ./lib/Fonts -DIR_GUI = ./lib/GUI +DIR_Config = ./lib/Config +DIR_EPD = ./lib/e-Paper +DIR_FONTS = ./lib/Fonts +DIR_GUI = ./lib/GUI DIR_Examples = ./examples -DIR_BIN = ./bin +DIR_BIN = ./bin -OBJ_C = $(wildcard ${DIR_EPD}/*.c ${DIR_GUI}/*.c ${DIR_Examples}/*.c ${DIR_FONTS}/*.c ) +EPD = NULL +ifeq ($(EPD), epd1in64g) + OBJ_C_EPD = ${DIR_EPD}/EPD_1in64g.c + OBJ_C_Examples = ${DIR_Examples}/EPD_1in64g_test.c +else ifeq ($(EPD), epd2in36g) + OBJ_C_EPD = ${DIR_EPD}/EPD_2in36g.c + OBJ_C_Examples = ${DIR_Examples}/EPD_2in36g_test.c +else ifeq ($(EPD), epd3in0g) + OBJ_C_EPD = ${DIR_EPD}/EPD_3in0g.c + OBJ_C_Examples = ${DIR_Examples}/EPD_3in0g_test.c +else ifeq ($(EPD), epd4in37g) + OBJ_C_EPD = ${DIR_EPD}/EPD_4in37g.c + OBJ_C_Examples = ${DIR_Examples}/EPD_4in37g_test.c +else ifeq ($(EPD), epd7in3g) + OBJ_C_EPD = ${DIR_EPD}/EPD_7in3g.c + OBJ_C_Examples = ${DIR_Examples}/EPD_7in3g_test.c +else ifeq ($(EPD), epd1in54des) + OBJ_C_EPD = ${DIR_EPD}/EPD_1in54_DES.c + OBJ_C_Examples = ${DIR_Examples}/EPD_1in54_DES_test.c +else ifeq ($(EPD), epd2in13des) + OBJ_C_EPD = ${DIR_EPD}/EPD_2in13_DES.c + OBJ_C_Examples = ${DIR_Examples}/EPD_2in13_DES_test.c +else ifeq ($(EPD), epd2in9des) + OBJ_C_EPD = ${DIR_EPD}/EPD_2in9_DES.c + OBJ_C_Examples = ${DIR_Examples}/EPD_2in9_DES_test.c +else ifeq ($(EPD), epd1in02d) + OBJ_C_EPD = ${DIR_EPD}/EPD_1in02d.c + OBJ_C_Examples = ${DIR_Examples}/EPD_1in02d_test.c +else ifeq ($(EPD), epd1in54) + OBJ_C_EPD = ${DIR_EPD}/EPD_1in54.c + OBJ_C_Examples = ${DIR_Examples}/EPD_1in54_test.c +else ifeq ($(EPD), epd1in54V2) + OBJ_C_EPD = ${DIR_EPD}/EPD_1in54_V2.c + OBJ_C_Examples = ${DIR_Examples}/EPD_1in54_V2_test.c +else ifeq ($(EPD), epd1in54b) + OBJ_C_EPD = ${DIR_EPD}/EPD_1in54b.c + OBJ_C_Examples = ${DIR_Examples}/EPD_1in54b_test.c +else ifeq ($(EPD), epd1in54bV2) + OBJ_C_EPD = ${DIR_EPD}/EPD_1in54b_V2.c + OBJ_C_Examples = ${DIR_Examples}/EPD_1in54b_V2_test.c +else ifeq ($(EPD), epd1in54c) + OBJ_C_EPD = ${DIR_EPD}/EPD_1in54c.c + OBJ_C_Examples = ${DIR_Examples}/EPD_1in54c_test.c +else ifeq ($(EPD), epd2in66) + OBJ_C_EPD = ${DIR_EPD}/EPD_2in66.c + OBJ_C_Examples = ${DIR_Examples}/EPD_2in66_test.c +else ifeq ($(EPD), epd2in66b) + OBJ_C_EPD = ${DIR_EPD}/EPD_2in66b.c + OBJ_C_Examples = ${DIR_Examples}/EPD_2in66b_test.c +else ifeq ($(EPD), epd2in7) + OBJ_C_EPD = ${DIR_EPD}/EPD_2in7.c + OBJ_C_Examples = ${DIR_Examples}/EPD_2in7_test.c +else ifeq ($(EPD), epd2in7V2) + OBJ_C_EPD = ${DIR_EPD}/EPD_2in7_V2.c + OBJ_C_Examples = ${DIR_Examples}/EPD_2in7_V2_test.c +else ifeq ($(EPD), epd2in7b) + OBJ_C_EPD = ${DIR_EPD}/EPD_2in7b.c + OBJ_C_Examples = ${DIR_Examples}/EPD_2in7b_test.c +else ifeq ($(EPD), epd2in7bV2) + OBJ_C_EPD = ${DIR_EPD}/EPD_2in7b_V2.c + OBJ_C_Examples = ${DIR_Examples}/EPD_2in7b_V2_test.c +else ifeq ($(EPD), epd2in9) + OBJ_C_EPD = ${DIR_EPD}/EPD_2in9.c + OBJ_C_Examples = ${DIR_Examples}/EPD_2in9_test.c +else ifeq ($(EPD), epd2in9V2) + OBJ_C_EPD = ${DIR_EPD}/EPD_2in9_V2.c + OBJ_C_Examples = ${DIR_Examples}/EPD_2in9_V2_test.c +else ifeq ($(EPD), epd2in9bc) + OBJ_C_EPD = ${DIR_EPD}/EPD_2in9bc.c + OBJ_C_Examples = ${DIR_Examples}/EPD_2in9bc_test.c +else ifeq ($(EPD), epd2in9bV3) + OBJ_C_EPD = ${DIR_EPD}/EPD_2in9b_V3.c + OBJ_C_Examples = ${DIR_Examples}/EPD_2in9b_V3_test.c +else ifeq ($(EPD), epd2in9d) + OBJ_C_EPD = ${DIR_EPD}/EPD_2in9d.c + OBJ_C_Examples = ${DIR_Examples}/EPD_2in9d_test.c +else ifeq ($(EPD), epd2in13) + OBJ_C_EPD = ${DIR_EPD}/EPD_2in13.c + OBJ_C_Examples = ${DIR_Examples}/EPD_2in13_test.c +else ifeq ($(EPD), epd2in13V2) + OBJ_C_EPD = ${DIR_EPD}/EPD_2in13_V2.c + OBJ_C_Examples = ${DIR_Examples}/EPD_2in13_V2_test.c +else ifeq ($(EPD), epd2in13V3) + OBJ_C_EPD = ${DIR_EPD}/EPD_2in13_V3.c + OBJ_C_Examples = ${DIR_Examples}/EPD_2in13_V3_test.c +else ifeq ($(EPD), epd2in13bc) + OBJ_C_EPD = ${DIR_EPD}/EPD_2in13bc.c + OBJ_C_Examples = ${DIR_Examples}/EPD_2in13bc_test.c +else ifeq ($(EPD), epd2in13bV3) + OBJ_C_EPD = ${DIR_EPD}/EPD_2in13b_V3.c + OBJ_C_Examples = ${DIR_Examples}/EPD_2in13b_V3_test.c +else ifeq ($(EPD), epd2in13bV4) + OBJ_C_EPD = ${DIR_EPD}/EPD_2in13b_V4.c + OBJ_C_Examples = ${DIR_Examples}/EPD_2in13b_V4_test.c +else ifeq ($(EPD), epd2in13d) + OBJ_C_EPD = ${DIR_EPD}/EPD_2in13d.c + OBJ_C_Examples = ${DIR_Examples}/EPD_2in13d_test.c +else ifeq ($(EPD), epd3in52) + OBJ_C_EPD = ${DIR_EPD}/EPD_3in52.c + OBJ_C_Examples = ${DIR_Examples}/EPD_3in52_test.c +else ifeq ($(EPD), epd3in7) + OBJ_C_EPD = ${DIR_EPD}/EPD_3in7.c + OBJ_C_Examples = ${DIR_Examples}/EPD_3in7_test.c +else ifeq ($(EPD), epd4in01f) + OBJ_C_EPD = ${DIR_EPD}/EPD_4in01f.c + OBJ_C_Examples = ${DIR_Examples}/EPD_4in01f_test.c +else ifeq ($(EPD), epd4in2) + OBJ_C_EPD = ${DIR_EPD}/EPD_4in2.c + OBJ_C_Examples = ${DIR_Examples}/EPD_4in2_test.c +else ifeq ($(EPD), epd4in2V2) + OBJ_C_EPD = ${DIR_EPD}/EPD_4in2_V2.c + OBJ_C_Examples = ${DIR_Examples}/EPD_4in2_V2_test.c +else ifeq ($(EPD), epd4in2bc) + OBJ_C_EPD = ${DIR_EPD}/EPD_4in2bc.c + OBJ_C_Examples = ${DIR_Examples}/EPD_4in2bc_test.c +else ifeq ($(EPD), epd4in2bV2) + OBJ_C_EPD = ${DIR_EPD}/EPD_4in2b_V2.c + OBJ_C_Examples = ${DIR_Examples}/EPD_4in2b_V2_test.c +else ifeq ($(EPD), epd4in37b) + OBJ_C_EPD = ${DIR_EPD}/EPD_4in37b.c + OBJ_C_Examples = ${DIR_Examples}/EPD_4in37b_test.c +else ifeq ($(EPD), epd5in65f) + OBJ_C_EPD = ${DIR_EPD}/EPD_5in65f.c + OBJ_C_Examples = ${DIR_Examples}/EPD_5in65f_test.c +else ifeq ($(EPD), epd5in83) + OBJ_C_EPD = ${DIR_EPD}/EPD_5in83.c + OBJ_C_Examples = ${DIR_Examples}/EPD_5in83_test.c +else ifeq ($(EPD), epd5in83V2) + OBJ_C_EPD = ${DIR_EPD}/EPD_5in83_V2.c + OBJ_C_Examples = ${DIR_Examples}/EPD_5in83_V2_test.c +else ifeq ($(EPD), epd5in83bc) + OBJ_C_EPD = ${DIR_EPD}/EPD_5in83bc.c + OBJ_C_Examples = ${DIR_Examples}/EPD_5in83bc_test.c +else ifeq ($(EPD), epd5in83bV2) + OBJ_C_EPD = ${DIR_EPD}/EPD_5in83b_V2.c + OBJ_C_Examples = ${DIR_Examples}/EPD_5in83b_V2_test.c +else ifeq ($(EPD), epd5in84) + OBJ_C_EPD = ${DIR_EPD}/EPD_5in84.c + OBJ_C_Examples = ${DIR_Examples}/EPD_5in84_test.c +else ifeq ($(EPD), epd7in5) + OBJ_C_EPD = ${DIR_EPD}/EPD_7in5.c + OBJ_C_Examples = ${DIR_Examples}/EPD_7in5_test.c +else ifeq ($(EPD), epd7in5V2) + OBJ_C_EPD = ${DIR_EPD}/EPD_7in5_V2.c + OBJ_C_Examples = ${DIR_Examples}/EPD_7in5_V2_test.c +else ifeq ($(EPD), epd7in5bc) + OBJ_C_EPD = ${DIR_EPD}/EPD_7in5bc.c + OBJ_C_Examples = ${DIR_Examples}/EPD_7in5bc_test.c +else ifeq ($(EPD), epd7in5bV2) + OBJ_C_EPD = ${DIR_EPD}/EPD_7in5b_V2.c + OBJ_C_Examples = ${DIR_Examples}/EPD_7in5b_V2_test.c +else ifeq ($(EPD), epd7in5HD) + OBJ_C_EPD = ${DIR_EPD}/EPD_7in5_HD.c + OBJ_C_Examples = ${DIR_Examples}/EPD_7in5_HD_test.c +else ifeq ($(EPD), epd7in5bHD) + OBJ_C_EPD = ${DIR_EPD}/EPD_7in5b_HD.c + OBJ_C_Examples = ${DIR_Examples}/EPD_7in5b_HD_test.c +else ifeq ($(EPD), epd10in2b) + OBJ_C_EPD = ${DIR_EPD}/EPD_10in2b.c + OBJ_C_Examples = ${DIR_Examples}/EPD_10in2b_test.c +else ifeq ($(EPD), epd13in3) + OBJ_C_EPD = ${DIR_EPD}/EPD_13in3.c + OBJ_C_Examples = ${DIR_Examples}/EPD_13in3_test.c +else + OBJ_C_EPD = NULL + OBJ_C_Examples = NULL +endif + +OBJ_C = $(wildcard ${OBJ_C_EPD} ${DIR_GUI}/*.c ${OBJ_C_Examples} ${DIR_Examples}/main.c ${DIR_Examples}/ImageData2.c ${DIR_Examples}/ImageData.c ${DIR_FONTS}/*.c ) OBJ_O = $(patsubst %.c,${DIR_BIN}/%.o,$(notdir ${OBJ_C})) RPI_DEV_C = $(wildcard $(DIR_BIN)/dev_hardware_SPI.o $(DIR_BIN)/RPI_sysfs_gpio.o $(DIR_BIN)/DEV_Config.o ) JETSON_DEV_C = $(wildcard $(DIR_BIN)/sysfs_software_spi.o $(DIR_BIN)/sysfs_gpio.o $(DIR_BIN)/DEV_Config.o ) @@ -19,20 +187,20 @@ USELIB_RPI = USE_BCM2835_LIB LIB_RPI=-Wl,--gc-sections ifeq ($(USELIB_RPI), USE_BCM2835_LIB) - LIB_RPI += -lbcm2835 -lm + LIB_RPI += -lbcm2835 -lm else ifeq ($(USELIB_RPI), USE_WIRINGPI_LIB) - LIB_RPI += -lwiringPi -lm + LIB_RPI += -lwiringPi -lm else ifeq ($(USELIB_RPI), USE_DEV_LIB) - LIB_RPI += -lm + LIB_RPI += -lm endif DEBUG_RPI = -D $(USELIB_RPI) -D RPI USELIB_JETSONI = USE_DEV_LIB # USELIB_JETSONI = USE_HARDWARE_LIB ifeq ($(USELIB_JETSONI), USE_DEV_LIB) - LIB_JETSONI = -lm + LIB_JETSONI = -lm else ifeq ($(USELIB_JETSONI), USE_HARDWARE_LIB) - LIB_JETSONI = -lm + LIB_JETSONI = -lm endif DEBUG_JETSONI = -D $(USELIB_JETSONI) -D JETSON @@ -41,7 +209,6 @@ DEBUG_JETSONI = -D $(USELIB_JETSONI) -D JETSON RPI:RPI_DEV RPI_epd JETSON: JETSON_DEV JETSON_epd -EPD = NULL TARGET = epd CC = gcc MSG = -g -O -ffunction-sections -fdata-sections -Wall @@ -50,7 +217,7 @@ CFLAGS += $(MSG) -D $(EPD) RPI_epd:${OBJ_O} echo $(@) $(CC) $(CFLAGS) -D RPI $(OBJ_O) $(RPI_DEV_C) -o $(TARGET) $(LIB_RPI) $(DEBUG) - + JETSON_epd:${OBJ_O} echo $(@) $(CC) $(CFLAGS) $(OBJ_O) $(JETSON_DEV_C) -o $(TARGET) $(LIB_JETSONI) $(DEBUG) @@ -58,26 +225,26 @@ JETSON_epd:${OBJ_O} $(shell mkdir -p $(DIR_BIN)) ${DIR_BIN}/%.o:$(DIR_Examples)/%.c - $(CC) $(CFLAGS) -c $< -o $@ -I $(DIR_Config) -I $(DIR_GUI) -I $(DIR_EPD) $(DEBUG) - + $(CC) $(CFLAGS) -c $< -o $@ -I $(DIR_Config) -I $(DIR_GUI) -I $(DIR_EPD) $(DEBUG) + ${DIR_BIN}/%.o:$(DIR_EPD)/%.c - $(CC) $(CFLAGS) -c $< -o $@ -I $(DIR_Config) $(DEBUG) - + $(CC) $(CFLAGS) -c $< -o $@ -I $(DIR_Config) $(DEBUG) + ${DIR_BIN}/%.o:$(DIR_FONTS)/%.c - $(CC) $(CFLAGS) -c $< -o $@ $(DEBUG) - + $(CC) $(CFLAGS) -c $< -o $@ $(DEBUG) + ${DIR_BIN}/%.o:$(DIR_GUI)/%.c - $(CC) $(CFLAGS) -c $< -o $@ -I $(DIR_Config) $(DEBUG) + $(CC) $(CFLAGS) -c $< -o $@ -I $(DIR_Config) $(DEBUG) RPI_DEV: - $(CC) $(CFLAGS) $(DEBUG_RPI) -c $(DIR_Config)/dev_hardware_SPI.c -o $(DIR_BIN)/dev_hardware_SPI.o $(LIB_RPI) $(DEBUG) - $(CC) $(CFLAGS) $(DEBUG_RPI) -c $(DIR_Config)/RPI_sysfs_gpio.c -o $(DIR_BIN)/RPI_sysfs_gpio.o $(LIB_RPI) $(DEBUG) - $(CC) $(CFLAGS) $(DEBUG_RPI) -c $(DIR_Config)/DEV_Config.c -o $(DIR_BIN)/DEV_Config.o $(LIB_RPI) $(DEBUG) + $(CC) $(CFLAGS) $(DEBUG_RPI) -c $(DIR_Config)/dev_hardware_SPI.c -o $(DIR_BIN)/dev_hardware_SPI.o $(LIB_RPI) $(DEBUG) + $(CC) $(CFLAGS) $(DEBUG_RPI) -c $(DIR_Config)/RPI_sysfs_gpio.c -o $(DIR_BIN)/RPI_sysfs_gpio.o $(LIB_RPI) $(DEBUG) + $(CC) $(CFLAGS) $(DEBUG_RPI) -c $(DIR_Config)/DEV_Config.c -o $(DIR_BIN)/DEV_Config.o $(LIB_RPI) $(DEBUG) JETSON_DEV: - $(CC) $(CFLAGS) $(DEBUG_JETSONI) -c $(DIR_Config)/sysfs_software_spi.c -o $(DIR_BIN)/sysfs_software_spi.o $(LIB_JETSONI) $(DEBUG) - $(CC) $(CFLAGS) $(DEBUG_JETSONI) -c $(DIR_Config)/sysfs_gpio.c -o $(DIR_BIN)/sysfs_gpio.o $(LIB_JETSONI) $(DEBUG) - $(CC) $(CFLAGS) $(DEBUG_JETSONI) -c $(DIR_Config)/DEV_Config.c -o $(DIR_BIN)/DEV_Config.o $(LIB_JETSONI) $(DEBUG) + $(CC) $(CFLAGS) $(DEBUG_JETSONI) -c $(DIR_Config)/sysfs_software_spi.c -o $(DIR_BIN)/sysfs_software_spi.o $(LIB_JETSONI) $(DEBUG) + $(CC) $(CFLAGS) $(DEBUG_JETSONI) -c $(DIR_Config)/sysfs_gpio.c -o $(DIR_BIN)/sysfs_gpio.o $(LIB_JETSONI) $(DEBUG) + $(CC) $(CFLAGS) $(DEBUG_JETSONI) -c $(DIR_Config)/DEV_Config.c -o $(DIR_BIN)/DEV_Config.o $(LIB_JETSONI) $(DEBUG) clean : rm $(DIR_BIN)/*.* diff --git a/RaspberryPi_JetsonNano/c/Makefile.save b/RaspberryPi_JetsonNano/c/Makefile.save deleted file mode 100644 index c927546..0000000 --- a/RaspberryPi_JetsonNano/c/Makefile.save +++ /dev/null @@ -1,82 +0,0 @@ -DIR_Config = ./lib/Config -DIR_EPD = ./lib/e-Paper -DIR_FONTS = ./lib/Fonts -DIR_GUI = ./lib/GUI -DIR_Examples = ./examples -DIR_BIN = ./bin - -OBJ_C = $(wildcard ${DIR_EPD}/*.c ${DIR_GUI}/*.c ${DIR_Examples}/*.c ${DIR_FONTS}/*.c ) -OBJ_O = $(patsubst %.c,${DIR_BIN}/%.o,$(notdir ${OBJ_C})) -RPI_DEV_C = $(wildcard $(DIR_BIN)/dev_hardware_SPI.o $(DIR_BIN)/RPI_sysfs_gpio.o $(DIR_BIN)/DEV_Config.o ) -JETSON_DEV_C = $(wildcard $(DIR_BIN)/sysfs_software_spi.o $(DIR_BIN)/sysfs_gpio.o $(DIR_BIN)/DEV_Config.o ) - -$(shell if[! -e $(DIR_BIN)];then mkdir -p $(DIR_BIN); fi) -$(shell if[! -e $(DIR_BIN)];then mkdir -p $(DIR_BIN); fi) -DEBUG = -D DEBUG - -# USELIB_RPI = USE_BCM2835_LIB -USELIB_RPI = USE_WIRINGPI_LIB -# USELIB_RPI = USE_DEV_LIB - -ifeq ($(USELIB_RPI), USE_BCM2835_LIB) - LIB_RPI = -lbcm2835 -lm -else ifeq ($(USELIB_RPI), USE_WIRINGPI_LIB) - LIB_RPI = -lwiringPi -lm -else ifeq ($(USELIB_RPI), USE_DEV_LIB) - LIB_RPI = -lm -endif -DEBUG_RPI = -D $(USELIB_RPI) -D RPI - -USELIB_JETSONI = USE_DEV_LIB -# USELIB_JETSONI = USE_HARDWARE_LIB -ifeq ($(USELIB_JETSONI), USE_DEV_LIB) - LIB_JETSONI = -lm -else ifeq ($(USELIB_JETSONI), USE_HARDWARE_LIB) - LIB_JETSONI = -lm -endif -DEBUG_JETSONI = -D $(USELIB_JETSONI) -D JETSON - -.PHONY : RPI JETSON clean - -RPI:RPI_DEV RPI_epd -JETSON: JETSON_DEV JETSON_epd - -TARGET = epd -CC = gcc -MSG = -g -O0 -Wall -CFLAGS += $(MSG) - -RPI_epd:${OBJ_O} - echo $(@) - $(CC) $(CFLAGS) -D RPI $(OBJ_O) $(RPI_DEV_C) -o $(TARGET) $(LIB_RPI) $(DEBUG) - -JETSON_epd:${OBJ_O} - echo $(@) - $(CC) $(CFLAGS) $(OBJ_O) $(JETSON_DEV_C) -o $(TARGET) $(LIB_JETSONI) $(DEBUG) - -${DIR_BIN}/%.o:$(DIR_Examples)/%.c - $(CC) $(CFLAGS) -c $< -o $@ -I $(DIR_Config) -I $(DIR_GUI) -I $(DIR_EPD) $(DEBUG) - -${DIR_BIN}/%.o:$(DIR_EPD)/%.c - $(CC) $(CFLAGS) -c $< -o $@ -I $(DIR_Config) $(DEBUG) - -${DIR_BIN}/%.o:$(DIR_FONTS)/%.c - $(CC) $(CFLAGS) -c $< -o $@ $(DEBUG) - -${DIR_BIN}/%.o:$(DIR_GUI)/%.c - $(CC) $(CFLAGS) -c $< -o $@ -I $(DIR_Config) $(DEBUG) - -RPI_DEV: - $(CC) $(CFLAGS) $(DEBUG_RPI) -c $(DIR_Config)/dev_hardware_SPI.c -o $(DIR_BIN)/dev_hardware_SPI.o $(LIB_RPI) $(DEBUG) - $(CC) $(CFLAGS) $(DEBUG_RPI) -c $(DIR_Config)/RPI_sysfs_gpio.c -o $(DIR_BIN)/RPI_sysfs_gpio.o $(LIB_RPI) $(DEBUG) - $(CC) $(CFLAGS) $(DEBUG_RPI) -c $(DIR_Config)/DEV_Config.c -o $(DIR_BIN)/DEV_Config.o $(LIB_RPI) $(DEBUG) - -JETSON_DEV: - $(CC) $(CFLAGS) $(DEBUG_JETSONI) -c $(DIR_Config)/sysfs_software_spi.c -o $(DIR_BIN)/sysfs_software_spi.o $(LIB_JETSONI) $(DEBUG) - $(CC) $(CFLAGS) $(DEBUG_JETSONI) -c $(DIR_Config)/sysfs_gpio.c -o $(DIR_BIN)/sysfs_gpio.o $(LIB_JETSONI) $(DEBUG) - $(CC) $(CFLAGS) $(DEBUG_JETSONI) -c $(DIR_Config)/DEV_Config.c -o $(DIR_BIN)/DEV_Config.o $(LIB_JETSONI) $(DEBUG) - -clean : - rm $(DIR_BIN)/*.* - rm $(TARGET) - diff --git a/RaspberryPi_JetsonNano/c/examples/main.c b/RaspberryPi_JetsonNano/c/examples/main.c index 8b4e64e..47c0fbc 100644 --- a/RaspberryPi_JetsonNano/c/examples/main.c +++ b/RaspberryPi_JetsonNano/c/examples/main.c @@ -15,173 +15,173 @@ int main(void) { // Exception handling:ctrl + c signal(SIGINT, Handler); - -#ifdef _1in64g + +#ifdef epd1in64g EPD_1in64g_test(); - -#elif _2in36g + +#elif epd2in36g EPD_2in36g_test(); - -#elif _3in0g + +#elif epd3in0g EPD_3in0g_test(); - -#elif _4in37g + +#elif epd4in37g EPD_4in37g_test(); - -#elif _7in3g + +#elif epd7in3g EPD_7in3g_test(); - -#elif _1in54des - EPD_1in54_DES_test(); - -#elif _2in13des - EPD_2in13_DES_test(); - -#elif _2in9des - EPD_2in9_DES_test(); - -#elif _1in02d + +#elif epd1in54des + EPD_1in54_DES_test(); + +#elif epd2in13des + EPD_2in13_DES_test(); + +#elif epd2in9des + EPD_2in9_DES_test(); + +#elif epd1in02d EPD_1in02d_test(); - -#elif _1in54 + +#elif epd1in54 EPD_1in54_test(); - -#elif _1in54V2 + +#elif epd1in54V2 EPD_1in54_V2_test(); - -#elif _1in54b + +#elif epd1in54b EPD_1in54b_test(); - -#elif _1in54bV2 + +#elif epd1in54bV2 EPD_1in54b_V2_test(); - -#elif _1in54c + +#elif epd1in54c EPD_1in54c_test(); - -#elif _2in66 - EPD_2in66_test(); - -#elif _2in66b - EPD_2in66b_test(); - -#elif _2in7 + +#elif epd2in66 + EPD_2in66_test(); + +#elif epd2in66b + EPD_2in66b_test(); + +#elif epd2in7 EPD_2in7_test(); - -#elif _2in7V2 - EPD_2in7_V2_test(); - -#elif _2in7b + +#elif epd2in7V2 + EPD_2in7_V2_test(); + +#elif epd2in7b EPD_2in7b_test(); - -#elif _2in7bV2 - EPD_2in7b_V2_test(); - -#elif _2in9 + +#elif epd2in7bV2 + EPD_2in7b_V2_test(); + +#elif epd2in9 EPD_2in9_test(); - -#elif _2in9V2 - EPD_2in9_V2_test(); - -#elif _2in9bc + +#elif epd2in9V2 + EPD_2in9_V2_test(); + +#elif epd2in9bc EPD_2in9bc_test(); - -#elif _2in9bV3 + +#elif epd2in9bV3 EPD_2in9b_V3_test(); - -#elif _2in9d + +#elif epd2in9d EPD_2in9d_test(); - -#elif _2in13 + +#elif epd2in13 EPD_2in13_test(); - -#elif _2in13V2 - EPD_2in13_V2_test(); - -#elif _2in13V3 - EPD_2in13_V3_test(); - -#elif _2in13bc + +#elif epd2in13V2 + EPD_2in13_V2_test(); + +#elif epd2in13V3 + EPD_2in13_V3_test(); + +#elif epd2in13bc EPD_2in13bc_test(); - -#elif _2in13bV3 + +#elif epd2in13bV3 EPD_2in13b_V3_test(); - -#elif _2in13bV4 - EPD_2in13b_V4_test(); - -#elif _2in13d + +#elif epd2in13bV4 + EPD_2in13b_V4_test(); + +#elif epd2in13d EPD_2in13d_test(); - -#elif _3in52 + +#elif epd3in52 EPD_3in52_test(); - -#elif _3in7 + +#elif epd3in7 EPD_3in7_test(); - -#elif _4in01f - EPD_4in01f_test(); - -#elif _4in2 + +#elif epd4in01f + EPD_4in01f_test(); + +#elif epd4in2 EPD_4in2_test(); - -#elif _4in2V2 - EPD_4in2_V2_test(); - -#elif _4in2bc + +#elif epd4in2V2 + EPD_4in2_V2_test(); + +#elif epd4in2bc EPD_4in2bc_test(); - -#elif _4in2bV2 + +#elif epd4in2bV2 EPD_4in2b_V2_test(); - -#elif _4in37b - EPD_4in37b_test(); - -#elif _5in65f - EPD_5in65f_test(); - -#elif _5in83 + +#elif epd4in37b + EPD_4in37b_test(); + +#elif epd5in65f + EPD_5in65f_test(); + +#elif epd5in83 EPD_5in83_test(); - -#elif _5in83V2 + +#elif epd5in83V2 EPD_5in83_V2_test(); - -#elif _5in83bc + +#elif epd5in83bc EPD_5in83bc_test(); - -#elif _5in83bV2 + +#elif epd5in83bV2 EPD_5in83b_V2_test(); - -#elif _5in84 - EPD_5in84_test(); - -#elif _7in5 + +#elif epd5in84 + EPD_5in84_test(); + +#elif epd7in5 EPD_7in5_test(); - -#elif _7in5V2 + +#elif epd7in5V2 EPD_7in5_V2_test(); - -#elif _7in5bc + +#elif epd7in5bc EPD_7in5bc_test(); - -#elif _7in5bV2 + +#elif epd7in5bV2 EPD_7in5b_V2_test(); - -#elif _7in5HD + +#elif epd7in5HD EPD_7in5_HD_test(); - -#elif _7in5bHD + +#elif epd7in5bHD EPD_7in5b_HD_test(); - -#elif _10in2b - EPD_10in2b_test(); - -#elif _13in3 - EPD_13in3_test(); + +#elif epd10in2b + EPD_10in2b_test(); + +#elif epd13in3 + EPD_13in3_test(); #else - printf("Please specify the EPD model when making. \r\n"); - printf("Example: When you run the EPD_7in5_V2_test() program, input: sudo make clean && make -j6 EPD=_7in5V2 \r\n"); - printf("Don't know which program you need to run? Refer to the user manual (Wiki) and main.c \r\n"); + printf("Please specify the EPD model when making. \r\n"); + printf("Example: When you run the EPD_7in5_V2_test() program, input: sudo make clean && make EPD=epd7in5V2 \r\n"); + printf("Don't know which program you need to run? Refer to the user manual (Wiki) and main.c \r\n"); #endif - + return 0; } diff --git a/RaspberryPi_JetsonNano/c/lib/e-Paper/EPD_1in64g.c b/RaspberryPi_JetsonNano/c/lib/e-Paper/EPD_1in64g.c index 6c4a971..c83196b 100644 --- a/RaspberryPi_JetsonNano/c/lib/e-Paper/EPD_1in64g.c +++ b/RaspberryPi_JetsonNano/c/lib/e-Paper/EPD_1in64g.c @@ -82,14 +82,6 @@ static void EPD_1IN64G_ReadBusyH(void) } Debug("e-Paper busy H release\r\n"); } -static void EPD_1IN64G_ReadBusyL(void) -{ - Debug("e-Paper busy L\r\n"); - while(DEV_Digital_Read(EPD_BUSY_PIN)) { //LOW: idle, HIGH: busy - DEV_Delay_ms(5); - } - Debug("e-Paper busy L release\r\n"); -} /****************************************************************************** function : Turn On Display diff --git a/RaspberryPi_JetsonNano/c/lib/e-Paper/EPD_2in36g.c b/RaspberryPi_JetsonNano/c/lib/e-Paper/EPD_2in36g.c index cc3f757..6e81bcc 100644 --- a/RaspberryPi_JetsonNano/c/lib/e-Paper/EPD_2in36g.c +++ b/RaspberryPi_JetsonNano/c/lib/e-Paper/EPD_2in36g.c @@ -83,14 +83,6 @@ static void EPD_2IN36G_ReadBusyH(void) } Debug("e-Paper busy H release\r\n"); } -static void EPD_2IN36G_ReadBusyL(void) -{ - Debug("e-Paper busy L\r\n"); - while(DEV_Digital_Read(EPD_BUSY_PIN)) { //LOW: idle, HIGH: busy - DEV_Delay_ms(5); - } - Debug("e-Paper busy L release\r\n"); -} /****************************************************************************** function : Turn On Display diff --git a/RaspberryPi_JetsonNano/c/lib/e-Paper/EPD_3in0g.c b/RaspberryPi_JetsonNano/c/lib/e-Paper/EPD_3in0g.c index 7301de2..138565d 100644 --- a/RaspberryPi_JetsonNano/c/lib/e-Paper/EPD_3in0g.c +++ b/RaspberryPi_JetsonNano/c/lib/e-Paper/EPD_3in0g.c @@ -83,14 +83,6 @@ static void EPD_3IN0G_ReadBusyH(void) } Debug("e-Paper busy H release\r\n"); } -static void EPD_3IN0G_ReadBusyL(void) -{ - Debug("e-Paper busy L\r\n"); - while(DEV_Digital_Read(EPD_BUSY_PIN)) { //LOW: idle, HIGH: busy - DEV_Delay_ms(5); - } - Debug("e-Paper busy L release\r\n"); -} /****************************************************************************** function : Turn On Display diff --git a/RaspberryPi_JetsonNano/c/lib/e-Paper/EPD_4in37g.c b/RaspberryPi_JetsonNano/c/lib/e-Paper/EPD_4in37g.c index 9aa6e6d..a978651 100755 --- a/RaspberryPi_JetsonNano/c/lib/e-Paper/EPD_4in37g.c +++ b/RaspberryPi_JetsonNano/c/lib/e-Paper/EPD_4in37g.c @@ -83,14 +83,6 @@ static void EPD_4IN37G_ReadBusyH(void) } Debug("e-Paper busy H release\r\n"); } -static void EPD_4IN37G_ReadBusyL(void) -{ - Debug("e-Paper busy L\r\n"); - while(DEV_Digital_Read(EPD_BUSY_PIN)) { //LOW: idle, HIGH: busy - DEV_Delay_ms(5); - } - Debug("e-Paper busy L release\r\n"); -} /****************************************************************************** function : Turn On Display diff --git a/RaspberryPi_JetsonNano/c/lib/e-Paper/EPD_7in3g.c b/RaspberryPi_JetsonNano/c/lib/e-Paper/EPD_7in3g.c index b196cd2..1fda762 100644 --- a/RaspberryPi_JetsonNano/c/lib/e-Paper/EPD_7in3g.c +++ b/RaspberryPi_JetsonNano/c/lib/e-Paper/EPD_7in3g.c @@ -83,14 +83,6 @@ static void EPD_7IN3G_ReadBusyH(void) } Debug("e-Paper busy H release\r\n"); } -static void EPD_7IN3G_ReadBusyL(void) -{ - Debug("e-Paper busy L\r\n"); - while(DEV_Digital_Read(EPD_BUSY_PIN)) { //LOW: idle, HIGH: busy - DEV_Delay_ms(5); - } - Debug("e-Paper busy L release\r\n"); -} /****************************************************************************** function : Turn On Display diff --git a/RaspberryPi_JetsonNano/c/list.txt b/RaspberryPi_JetsonNano/c/list.txt index 32b3798..88409ea 100644 --- a/RaspberryPi_JetsonNano/c/list.txt +++ b/RaspberryPi_JetsonNano/c/list.txt @@ -1,46 +1,46 @@ EPD model EPD define (EPD=) -1.64inch e-Paper (G) _1in64g -2.36inch e-Paper (G) _2in36g -3inch e-Paper (G) _3in0g -4.37inch e-Paper (G) _4in37g -7.3inch e-Paper (G) _7in3g -1.54inch e-Paper (V2) _1in54V2 -1.54inch e-Paper (B) (V2) _1in54bV2 -1.54inch e-Paper (C) _1in54c -2.66inch e-Paper _2in66 -2.66inch e-Paper (B) _2in66b -2.7inch e-Paper _2in7 -2.7inch e-Paper (V2) _2in7V2 -2.9inch e-Paper (V2) _2in9V2 -2.9inch e-Paper (B)/(C) _2in9bc -2.9inch e-Paper (B) (V3) _2in9bV3 -2.9inch e-Paper (D) _2in9d -2.9inch e-Paper (V3) _2in13V3 -2.13inch e-Paper (B)/(C) _2in13bc -2.13inch e-Paper (B) (V3) _2in13bV3 -2.13inch e-Paper (B) (V4) _2in13bV4 -2.13inch e-Paper (D) _2in13d -3.52inch e-Paper _3in52 -3.7inch e-Paper _3in7 -4.01inch e-Paper (F) _4in01f -4.2inch e-Paper _4in2 -4.2inch e-Paper (V2 _4in2V2 -4.2inch e-Paper (B)/(C) _4in2bc -4.2inch e-Paper (B) (V2) _4in2bV2 -5.65inch e-Paper (F) _5in65f -5.83inch e-Paper (V2) _5in83V2 -5.83inch e-Paper (B)/(C) _5in83bc -5.83inch e-Paper (B) (V2) _5in83bV2 -7.5inch e-Paper (V2) _7in5V2 -7.5inch e-Paper (B)/(C) _7in5bc -7.5inch e-Paper (B) (V2) _7in5bV2 +1.64inch e-Paper (G) epd1in64g +2.36inch e-Paper (G) epd2in36g +3inch e-Paper (G) epd3in0g +4.37inch e-Paper (G) epd4in37g +7.3inch e-Paper (G) epd7in3g +1.54inch e-Paper (V2) epd1in54V2 +1.54inch e-Paper (B) (V2) epd1in54bV2 +1.54inch e-Paper (C) epd1in54c +2.66inch e-Paper epd2in66 +2.66inch e-Paper (B) epd2in66b +2.7inch e-Paper epd2in7 +2.7inch e-Paper (V2) epd2in7V2 +2.9inch e-Paper (V2) epd2in9V2 +2.9inch e-Paper (B)/(C) epd2in9bc +2.9inch e-Paper (B) (V3) epd2in9bV3 +2.9inch e-Paper (D) epd2in9d +2.9inch e-Paper (V3) epd2in13V3 +2.13inch e-Paper (B)/(C) epd2in13bc +2.13inch e-Paper (B) (V3) epd2in13bV3 +2.13inch e-Paper (B) (V4) epd2in13bV4 +2.13inch e-Paper (D) epd2in13d +3.52inch e-Paper epd3in52 +3.7inch e-Paper epd3in7 +4.01inch e-Paper (F) epd4in01f +4.2inch e-Paper epd4in2 +4.2inch e-Paper (V2 epd4in2V2 +4.2inch e-Paper (B)/(C) epd4in2bc +4.2inch e-Paper (B) (V2) epd4in2bV2 +5.65inch e-Paper (F) epd5in65f +5.83inch e-Paper (V2) epd5in83V2 +5.83inch e-Paper (B)/(C) epd5in83bc +5.83inch e-Paper (B) (V2) epd5in83bV2 +7.5inch e-Paper (V2) epd7in5V2 +7.5inch e-Paper (B)/(C) epd7in5bc +7.5inch e-Paper (B) (V2) epd7in5bV2 Add EPD define at compile time, for example: # modle is 7.5inch e-Paper (B) (V2) sudo make clean - sudo make -j4 EPD=_7in5bV2 + sudo make EPD=epd7in5bV2 编译的时候加上 EPD define,例如: # 屏幕型号为 7.5inch e-Paper (B) (V2) sudo make clean - sudo make -j4 EPD=_7in5bV2 + sudo make EPD=epd7in5bV2 diff --git a/RaspberryPi_JetsonNano/c/readme_CN.txt b/RaspberryPi_JetsonNano/c/readme_CN.txt index 435b0e2..787b19d 100644 --- a/RaspberryPi_JetsonNano/c/readme_CN.txt +++ b/RaspberryPi_JetsonNano/c/readme_CN.txt @@ -4,8 +4,8 @@ * | Function : Help with use * | Info : *---------------- -* | This version: V1.2 -* | Date : 2022-09-20 +* | This version: V1.3 +* | Date : 2022-10-13 * | Info : 在这里提供一个中文版本的使用文档,以便你的快速使用 ******************************************************************************/ 这个文件是帮助您使用本例程。 @@ -32,17 +32,17 @@ BUSY -> 24 你可以在main.c中看到许多测试函数和宏定义设置,在编译时指定屏幕对应的宏定义可以直接编译对应的测试程序。 请注意你购买的是哪一款的墨水屏。具体的对应关系可以查阅我们的Wiki和list.txt文件。 栗子1: - 如果你购买的3.7inch e-paper (V1),那么你应该在编译时加上 EPD=_3in7 + 如果你购买的3.7inch e-paper (V1),那么你应该在编译时加上 EPD=epd3in7 sudo make clean - sudo make -j4 EPD=_3in7 + sudo make EPD=epd3in7 栗子2: - 如果你购买的2.9inch e-paper (B) (V1),由于2.9寸的B型和C型是公用的驱动代码,那么你应该在编译时加上 EPD=_2in9bc + 如果你购买的2.9inch e-paper (B) (V1),由于2.9寸的B型和C型是公用的驱动代码,那么你应该在编译时加上 EPD=epd2in9bc sudo make clean - sudo make -j4 EPD=_2in9bc + sudo make EPD=epd2in9bc 栗子3: - 如果你购买的是7.5inch e-Paper (V2),那么你应该在编译时加上 EPD=_7in5V2 + 如果你购买的是7.5inch e-Paper (V2),那么你应该在编译时加上 EPD=epd7in5V2 sudo make clean - sudo make -j4 EPD=_7in5V2 + sudo make EPD=epd7in5V2 然后会生成可执行文件:epd 运行:sudo ./epd diff --git a/RaspberryPi_JetsonNano/c/readme_EN.txt b/RaspberryPi_JetsonNano/c/readme_EN.txt index 33c07f0..144fc7c 100644 --- a/RaspberryPi_JetsonNano/c/readme_EN.txt +++ b/RaspberryPi_JetsonNano/c/readme_EN.txt @@ -4,8 +4,8 @@ * | Function : Help with use * | Info : *---------------- -* | This version: V1.2 -* | Date : 2022-09-20 +* | This version: V1.3 +* | Date : 2022-10-13 * | Info : Here is an English version of the documentation for your quick use. ******************************************************************************/ This file is to help you use this routine. @@ -35,17 +35,17 @@ You can see many test functions and macro definition Settings in main.c. Specifying the macro definition for the EPD at compile time can directly compile the corresponding test program. Please pay attention to which type of ink screen you buy. For detailed correspondence, see our Wiki and list.txt file. Example 1: -     If you buy 3.7inch e-paper (V1) then you should add EPD=_3in7 at compile time +     If you buy 3.7inch e-paper (V1) then you should add EPD=epd3in7 at compile time sudo make clean - sudo make -j4 EPD=_3in7 + sudo make EPD=epd3in7 Example 2: - If you buy a 2.9-inch e-paper (B) (V1), you should add EPD= 2IN9bc at compile time since the 2.9-inch type B and Type C are common driver code + If you buy a 2.9-inch e-paper (B) (V1), you should add EPD=epd2IN9bc at compile time since the 2.9-inch type B and Type C are common driver code sudo make clean - sudo make -j4 EPD=_2in9bc + sudo make EPD=epd2in9bc Example 3: - If you buy a 7.5-inch e-paper (V2), you should add EPD=_7in5V2 at compile time + If you buy a 7.5-inch e-paper (V2), you should add EPD=epd7in5V2 at compile time sudo make clean - sudo make -j4 EPD=_7in5V2 + sudo make EPD=epd7in5V2 An executable file is then generated: epd Run: sudo ./epd